System Controller Clock Circuit
Sun Confidential: Internal Only
29
SunService Sun Microsystems, Inc. All Rights Reserved. Enterprise Services
System Controller Clock Circuit
The system controllers use a programmable clock. The clock generation
circuitry manufactures a base clock of 75 MHz.
In normal operation, each system controller sends its clocks to the phase
lock loop (PLL) circuitry in the clock control logic of the other system
controller. The clock control logic arbitrarily selects one of the System
controllers as the source of the active clocks for the platform.
Assuming you have both SCs present, during the boot sequence of the
SSC, you will get a messages indicating that clock failover is enabled.
Jun 06 10:32:23 4800a-sc0 Platform.SC: Clock failover enabled.
If one of the system controller board clock circuits fails, you will see a
message stating:
Jun 06 10:32:23 4800a-sc0 Platform.SC: Clock failover disabled.
The PLL circuitry in the other system controller will detect the failure and
present its clocks to the platform. The platform will source the clocks from
the remaining system controller without interruption to domain
operation.
A platform only needs one system controller. The other is there to
provide a redundant clock source to the platform, and to facilitate
system controller failover.
PLL
PLL
SC0
SC1
75MHz to
75MHz
75MHz
the platform
