Spectrum M2p.59 Series, Hardware Manual, Page: 99 / 190

Trigger modes and appendant registers Trigger masks
(c) Spectrum Instrumentation GmbH 99
The table below is showing the registers for the channel OR mask (A/D cards only) and the possible constants that can be written to it.
The following example shows, how to setup the OR mask for channel trigger. As an example a simple edge detection has been chosen. The
explanation and a detailed description of the different trigger modes for the channel trigger modes will be shown in the dedicated passage
within this chapter.
Trigger AND mask
The purpose of this passage is to explain the trigger AND mask (see
left figure) and all the appendant software registers in detail.
The AND mask shown in the overview before as one object, is sepa -
rated into two parts: a general AND mask for external trigger and
software trigger and a channel AND mask.
Every trigger source of the M2p series cards except the software trig -
ger is wired to one of the above mentioned AND masks. The user then can
program which trigger source will be recognized, and which one won’t.
This selection for the general mask is realized with the SPC_TRIG_ANDMASK
register in combination with constants for every possible trigger source.
This selection for the channel mask (A/D cards only) is realized with the SP -
C_TRIG_CH_ANDMASK0 register in combination with constants for every
possible channel trigger source.
In either case the sources are coded as a bitfield, so that they can be combined
by one access to the driver with the help of a bitwise OR.
Table 55: Spectrum API: channel trigger OR mask related software register and available settings
Register Value Direction Description
SPC_TRIG_CH_AVAILORMASK0 40450 read Bitmask, in which all bits of the below mentioned sources/channels (0…7) for the channel OR mask
are set, if available.
SPC_TRIG_CH_ORMASK0 40460 read/write Includes the analog channels (0…7) within the channel trigger OR mask of the card.
SPC_TMASK0_CH0 00000001h Enables channel0 for recognition within the channel OR mask.
SPC_TMASK0_CH1 00000002h Enables channel1 for recognition within the channel OR mask.
SPC_TMASK0_CH2 00000004h Enables channel2 for recognition within the channel OR mask.
SPC_TMASK0_CH3 00000008h Enables channel3 for recognition within the channel OR mask.
SPC_TMASK0_CH4 00000010h Enables channel4 for recognition within the channel OR mask.
SPC_TMASK0_CH5 00000020h Enables channel5 for recognition within the channel OR mask.
SPC_TMASK0_CH6 00000040h Enables channel6 for recognition within the channel OR mask.
SPC_TMASK0_CH7 00000080h Enables channel7 for recognition within the channel OR mask.
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_ORMASK, SPC_TMASK_NONE); // disable default software trigger
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_CH_ORMASK0, SPC_TMASK_CH0); // Enable channel0 trigger within the OR mask
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_CH0_LEVEL0, 0); // Trigger level is zero crossing
spcm_dwSetParam_i32 (hDrv, SPC_TRIG_CH0_MODE, SPC_TM_POS); // Setting up channel trigger for rising edges
Image 57: Trigger overview - trigger AND mask
Image 59: trigger AND mask details