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(c) Spectrum Instrumentation GmbH
Limits of pre trigger, post trigger, memory size
Mode Gated Sampling
Limits of pre trigger, post trigger, memory size
The maximum memory size parameter is only limited by the number of activated channels and by the amount of installed memory. Please
keep in mind that each samples needs 2 bytes of memory to be stored. Minimum memory size as well as minimum and maximum post trigger
limits are independent of the activated channels or the installed memory.
Due to the internal organization of the card memory there is a certain stepsize when setting these values that has to be taken into account.
The following table gives you an overview of all limits concerning pre trigger, post trigger, memory size, segment size and loops. The table
shows all values in relation to the installed memory size in samples. If more memory is installed the maximum memory size figures will increase
according to the complete installed memory
All figures listed here are given in samples. An entry of [8G - 16] means [8 GSamples - 16] = 8,589,934,576 samples.
The given memory and memory / divider figures depend on the installed on-board memory as listed below:
Table 82: Overview of all limits of pre-trigger, post-trigger and memory size for the different channel activations and acquisition modes
Activated
Used
Memory size
Pre trigger
Post trigger
Segment size
Loops
Channels
Mode
SPC_MEMSIZE
SPC_PRETRIGGER
SPC_POSTTRIGGER
SPC_SEGMENTSIZE
SPC_LOOPS
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
1 Ch
Standard Single
16
Mem
8
8
Mem - 8
8
8
8G - 8
8
not used
not used
(defined by mem and post)
Standard
Multi/ABA
16
Mem
8
8
32k
8
8
Mem - 8
8
16
Mem
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem
8
8
32k
8
8
Mem - 8
8
not used
not used
FIFO Single
not used
8
32k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
32k
8
8
8G - 8
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
32k
8
8
8G - 8
8
not used
0 (
)
4G - 1
1
2 Ch
Standard Single
16
Mem/2
8
8
Mem/2 - 8
8
8
8G - 8
8
not used
not used
(defined by mem and post)
Standard
Multi/ABA
16
Mem/2
8
8
16k
8
8
Mem/2 - 8
8
16
Mem/2
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem/2
8
8
16k
8
8
Mem/2 - 8
8
not used
not used
FIFO Single
not used
8
16k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
16k
8
8
8G - 8
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
16k
8
8
8G - 8
8
not used
0 (
)
4G - 1
1
4 Ch
Standard Single
16
Mem/4
8
8
Mem/4 - 8
8
8
8G - 16
8
not used
not used
(defined by mem and post)
Standard
Multi/ABA
16
Mem/4
8
8
8k
8
8
Mem/4 - 8
8
16
Mem/4
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem/4
8
8
8k
8
8
Mem/4 - 8
8
not used
not used
FIFO Single
not used
8
8k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
8k
8
8
8G - 16
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
8k
8
8
8G - 16
8
not used
0 (
)
4G - 1
1
8 Ch
Standard Single
16
Mem/8
8
8
Mem/8 - 8
8
8
8G - 8
8
not used
not used
(defined by mem and post)
Standard
Multi/ABA
16
Mem/8
8
8
4k
8
8
Mem/8 - 8
8
16
Mem/8
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem/8
8
8
4k
8
8
Mem/8 - 8
8
not used
not used
FIFO Single
not used
8
4k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
4k
8
8
8G - 16
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
4k
8
8
8G - 16
8
not used
0 (
)
4G - 1
1
Installed Memory
512 MSample
Mem
512 MSample
Mem/2
256 MSample
Mem/4
128 MSample
Mem/8
64 MSample
Summary of Contents for M2p.59 Series
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