Spectrum M2p.59 Series, Hardware Manual, Page: 93 / 190

Clock generation Overview
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Clock generation
Overview
The Spectrum M2p PCI Express (PCIe) cards offer a wide variety of differ -
ent clock modes to match all the customers needs. All of the clock modes
are described in detail with programming examples in this chapter.
The figure is showing an overview of the complete engine used on all M2p
cards for clock generation.
The purpose of this chapter is to give you a guide to the best matching
clock settings for your specific application and needs.
Clock Mode Register
The selection of the different clock modes has to be done by the SPC_CLOCKMODE register. All available modes, can be read out by the
help of the SPC_AVAILCLOCKMODES register.
The different clock modes and all other related or required register settings are described on the following pages.
The different clock modes
Standard internal sample rate (PLL with internal reference)
This is the easiest and most common way to generate a sample rate with no need for additional external clock signals. The sample rate has
a very fine resolution, low jitter and a high accuracy. The on-board oscillator acts as a reference to the internal PLL. The specification is found
in the technical data section of this manual.
Direct external clock
Any clock can be fed in that matches the specification of the board. The external clock signal can be used to synchronize the board on a
system clock or to feed in an exact matching sample rate.
External reference clock
Any clock can be fed in that matches the specification of the board. The external clock signal can be used to synchronize the board on a
system clock or to feed in an exact matching sample rate. The external clock is divided/multiplied using a PLL allowing a wide range of
external clock modes.
Synchronization Clock (option Star-Hub)
The Star-Hub option allows the synchronization of up to 16 cards of the M2p series from Spectrum with a minimal phase delay between the
different cards. The clock is distributed from the master card to all connected cards. As this clock is also available at the PLL input, cards of
the same or slower sampling speeds can be synchronized with different sample rates when using the PLL. For details on the synchronization
option please take a look at the dedicated chapter in this manual.
Standard internal sampling clock (PLL)
The internal sampling clock is generated in default mode by a programmable high precision quartz. You need to select the clock mode by
the dedicated register shown in the table below:
Table 44: Spectrum API: clock mode register and available clock modes
Register Value Direction Description
SPC_AVAILCLOCKMODES 20201 read Bitmask, in which all bits of the below mentioned clock modes are set, if available.
SPC_CLOCKMODE 20200 read/write Defines the used clock mode or reads out the actual selected one.
SPC_CM_INTPLL 1 Enables internal PLL with 20 MHz internal reference for sample clock generation.
SPC_CM_EXTERNAL 8 Enables external clock input for direct sample clock generation.
SPC_CM_EXTREFCLOCK 32 Enables internal PLL with external reference for sample clock generation.
Table 45: Spectrum API: clock mode software register and setting
Register Value Direction Description
SPC_CLOCKMODE 20200 read/write Defines the used clock mode
Image 53: Overview of M2p clock structure with optional star-hub