Acquisition modes
Buffer handling
(c) Spectrum Instrumentation GmbH
87
All figures listed here are given in samples. An entry of [8G - 16] means [8 GSamples - 16] = 8,589,934,576 samples.
The given memory and memory / divider figures depend on the installed on-board memory as listed below:
Please keep in mind that this table shows all values at once. Only the absolute maximum and minimum values are shown. There might be
additional limitations. Which of these values are programmed depends on the used mode. Please read the detailed documentation of the
mode.
Buffer handling
To handle the huge amount of data that can possibly be acquired with the M4i/M4x/M2p series cards, there is a very reliable two step
buffer strategy set up. The on-board memory of the card can be completely used as a real FIFO buffer. In addition a part of the PC memory
can be used as an additional software buffer. Transfer between hardware FIFO and software buffer is performed interrupt driven and auto
-
matically by the driver to get best performance. The following drawing will give you an overview of the structure of the data transfer handling:
Standard
Multi/ABA
16
Mem/4
8
8
8k
8
8
Mem/4 - 8
8
16
Mem/4
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem/4
8
8
8k
8
8
Mem/4 - 8
8
not used
not used
FIFO Single
not used
8
8k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
8k
8
8
8G - 16
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
8k
8
8
8G - 16
8
not used
0 (
)
4G - 1
1
8 Ch
Standard Single
16
Mem/8
8
8
Mem/8 - 8
8
8
8G - 8
8
not used
not used
(defined by mem and post)
Standard
Multi/ABA
16
Mem/8
8
8
4k
8
8
Mem/8 - 8
8
16
Mem/8
8
not used
(defined by segment and
post)
(Limited by max pretrigger)
Standard Gate
16
Mem/8
8
8
4k
8
8
Mem/8 - 8
8
not used
not used
FIFO Single
not used
8
4k
8
not used
16
8G - 16
8
0 (
)
4G - 1
1
FIFO Multi/ABA
not used
8
4k
8
8
8G - 16
8
16
pre+post
8
0 (
)
4G - 1
1
(defined by segment and
post)
(Limited by max pretrigger)
FIFO Gate
not used
8
4k
8
8
8G - 16
8
not used
0 (
)
4G - 1
1
Installed Memory
512 MSample
Mem
512 MSample
Mem/2
256 MSample
Mem/4
128 MSample
Mem/8
64 MSample
Table 39: Overview of all limits of pre-trigger, post-trigger and memory size for the different channel activations and acquisition modes
Activated
Used
Memory size
Pre trigger
Post trigger
Segment size
Loops
Channels
Mode
SPC_MEMSIZE
SPC_PRETRIGGER
SPC_POSTTRIGGER
SPC_SEGMENTSIZE
SPC_LOOPS
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
Image 52: Overview of buffer handling for DMA transfers showing and the interaction with the DMA engine
Summary of Contents for M2p.59 Series
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