Siemens SAB 80515 Series, User Manual, Page: 56 / 270

Semiconductor Group 56
On-Chip Peripheral Components
Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to-
SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX
control block that a transmission is requested. Transmission actually commences at S1P1 of the
machine cycle following the next roll-over in the divide-by-16 counter (thus, the bit times are
synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal).
The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later,
DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift
pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte
is at the output position of the shift register, then the 1 that was initially loaded into the 9th position,
is just left of the MSB, and all positions to the left of that contain zero. This condition flags the TX
control to do one last shift and then deactivates SEND and sets TI. This occurs at the 10th divide-
by-16 rollover after "write-to-SBUF".
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a
rate of 16 times whatever baud rate has been established. When a reception is detected, the divide-
by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the
divide-by-16 counter aligns its rollover with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16 counter states. At the 7th, 8th and 9th
counter state of each bit time, the bit detector samples the value of RxD. The value accepted is the
value that was seen in at least 2 of the 3 samples. This is done for noise rejection. lf the value
accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking
for another 1-to-0 transition. This is to provide rejection of false start bits. lf the start bit proves valid,
it is shifted into the input shift register, and reception of the rest of the frame will proceed.
As data bits come from the right, 1’s shift out to the left. When the start bit arrives at the leftmost
position in the shift register (which in mode 1 is a 9-bit register), it flags the RX control block to do
one last shift. The signal to load SBUF and RB8 and to set RI will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated:
1) RI = 0, and
2) either SM2 = 0 or the received stop bit = 1
lf either of these two conditions is not met the received frame is irretrievably lost. lf both conditions
are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time,
no matter whether the above conditions are met or not, the unit goes back to looking for a 1-to-0
transition in RxD.
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