Semiconductor Group
26
Memory Organization
Datapointer, SFR Address 082H and 083H
The 16-bit Datapointer (DPTR) register is a concatenation of registers DPH (data pointer’s high
order byte) and DPL (data pointer’s low order byte). The data pointer is used in register-indirect
addressing to move program memory constants and external data memory variables, as well as to
branch within the 64 Kbyte program memory address space.
Ports 0 to 5
P0 to P5 are the SFR latches to port 0 to 5, respectively. The port SFRs 0 to 5 are bit-addressable.
Ports 0 to 5 are 8-bit I/O ports (that is in total 48 I/O lines) which may be used as general purpose
ports and which provide alternate output functions dedicated to the on-chip peripherals of the SAB
80(C)515.
Port 6 (AN0 to AN7)
In the MYMOS versions, the analog input lines AN0 to AN7 can only be used as inputs for the A/D
converter.
In the ACMCS versions these lines may also be used as digital inputs. In this case they are
addressed as an additional input port (port 6) via special function register P6 (0DBH). Since port 6
has no internal latch, the contents of SFR P6 only depends on the levels applied to the input lines.
For details about this port please refer to section 7.1 (Parallel I/O).
Peripheral Control, Data and Status Registers
Most of the special function registers are used as control, status, and data registers to handle the
on-chip peripherals.
In the special function register table the register names are organized in groups and each of these
groups refer to one peripheral unit. More details on how to program these registers are given in the
descriptions of the following peripheral units:
Unit
Symbol
Section
Ports
–
7.1
Serial Channel
–
7.2
Timer 0/1
–
7.3
A/D-Converter
ADC
7.4
Timer 2 with Comp/Capt/Reload
CCU
7.5
Power Saving Modes
–
7.6
Watchdog Timer
WDT
7.7
Interrupt System
–
8
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Summary of Contents for SAB 80515 Series
Page 9: ...Semiconductor Group 9 Introduction Figure 1 2 Block Diagram ...
Page 12: ...Semiconductor Group 12 Fundamental Structure Figure 2 1 Detailed Block Diagram ...
Page 18: ...Semiconductor Group 18 Central Processing Unit Figure 3 1 Fetch Execute Sequence ...
Page 73: ...Semiconductor Group 73 On Chip Peripheral Components Figure 7 25 A D Converter Block Diagram ...
Page 83: ...Semiconductor Group 83 On Chip Peripheral Components Figure 7 33 a Timer 2 Block Diagram ...
Page 215: ...Device Specifications Semiconductor Group 215 ...
Page 217: ...Device Specifications Semiconductor Group 217 Pin Configuration P LCC 68 ...
Page 219: ...Device Specifications Semiconductor Group 219 Logic Symbol ...
Page 226: ...Device Specifications Semiconductor Group 226 Figure 1 Block Diagram ...
Page 229: ...Device Specifications Semiconductor Group 229 Figure 2 Memory Address Spaces ...
Page 239: ...Device Specifications Semiconductor Group 239 Figure 4 Block Diagram of the A D Converter ...
Page 241: ...Device Specifications Semiconductor Group 241 Figure 5 Interrupt Request Sources ...
Page 242: ...Device Specifications Semiconductor Group 242 Figure 6 Interrupt Priority Level Structure ...