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Semiconductor Group

20

Memory Organization

For details about the addressing modes see chapter 9.1.    

    

Figure 4-1
Program Memory Address Space    

The lower 128 bytes of the internal RAM are again grouped in three address spaces
(see figure 4-3):

1)

A general purpose register area occupies locations 0 through 1FH (see also section 4.3).

2)

The next 16 bytes, location 20H through 2FH, contain 128 directly addressable bits.
Programming information: These bits can be referred to in two ways, both of which are
acceptable for the ASM51. One way is to refer to their bit addresses, i.e. 0 to 7FH. The other
way is by referencing to bytes 20H to 2FH. Thus bits 0 to 7 can also be referred to as bits 20.0
to 20.7, and bits 08H and 0FH are the same as 21.0 to 21.7 and so on. Each of the 16 bytes in
this segment may also be addressed as a byte.)

3)

Locations 30H to 7FH can be used as a scratch pad area.

Address Space

Locations

Addressing Mode

Lower 128 bytes of RAM

00H to 7FH

direct/indirect

Upper 128 bytes of RAM

80H to 0FFH

indirect

Special function registers

80H to 0FFH

direct

*

Summary of Contents for SAB 80515 Series

Page 1: ...User s Manual 08 95 Microcomputer Components SAB 80515 SAB 80C515 8 Bit Single Chip Microcontroller Family ...

Page 2: ... we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components1 of the Semiconductor Group of Siemens AG may only be used in life support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG 1 A critical component is a component used in a life suppor...

Page 3: ... 2 Data Memory 19 4 3 General Purpose Register 23 4 4 Special Function Registers 23 5 External Bus Interface 27 5 1 Accessing External Memory 27 5 2 PSEN Program Store Enable 29 5 3 ALE Address Latch Enable 29 5 4 Overlapping External Data and Program Memory Spaces 29 6 System Reset 31 6 1 Hardware Reset and Power Up Reset 31 6 1 1 Reset Function and Circuitries 31 6 1 2 Hardware Reset Timing 34 7...

Page 4: ...nverter 72 7 4 1 Function and Control 74 7 4 1 1 lnitialization and Input Channel Selection 74 7 4 1 2 Start of Conversion 75 7 4 2 Reference Voltages 76 7 4 3 A D Converter Timing 80 7 5 Timer 2 with Additional Compare Capture Reload 82 7 5 1 Timer 2 85 7 5 2 Compare Function of Registers CRC CC1 to CC3 88 7 5 2 1 Compare Mode 0 88 7 5 2 2 Compare Mode 1 92 7 5 2 3 Using Interrupts in Combination...

Page 5: ...m External Source 109 7 9 System Clock Output 110 8 Interrupt System 112 8 1 Interrupt Structure 112 8 2 Priority Level Structure 120 8 3 How Interrupts are Handled 122 8 4 External Interrupts 125 8 5 Response Time 126 9 Instruction Set 127 9 1 Addressing Modes 127 9 2 Introduction to the Instruction Set 129 9 2 1 Data Transfer 129 9 2 2 Arithmetic 130 9 2 3 Logic 132 9 2 4 Control Transfer 132 9 ...

Page 6: ...except that it lacks the on chip program memory The SAB 80 C 515 80 C 535 is supplied in a 68 pin plastic leaded chip carrier package P LCC 68 In addition to the standard temperature range version 0 to 70 C there are also versions for extended temperature ranges available see data sheets Functional Description The members of the SAB 80515 family of microcontrollers are SAB 80C515 Microcontroller d...

Page 7: ...bit watchdog timer Power down supply for 40 byte of RAM Boolean processor 256 directly addressable bits 12 interrupt sources 7 external 5 internal 4 priority levels Stack depth up to 256 byte 1 µs instruction cycle at 12 MHz operation 4 µs multiply and divide External program and data memory expandable up to 64 Kbyte each Compatible with standard SAB 8080 8085 peripherals and memories Space saving...

Page 8: ...Semiconductor Group 8 Introduction Figure 1 1 shows the logic symbol figure 1 2 the block diagram of the SAB 80 C 515 Figure 1 1 Logic Symbol ...

Page 9: ...Semiconductor Group 9 Introduction Figure 1 2 Block Diagram ...

Page 10: ...ll kinds of digital signal processing Figure 2 1 shows a block diagram of the SAB 80 C 515 80 C 535 The SAB 80C515 80C535 combines the powerful architecture of the industry standard controller SAB 80515 80535 with the advantages of the ACMOS technology e g power saving modes The differences between MYMOS and ACMOS components are explained in section 2 1 Readers who are familiar with the SAB 8051 m...

Page 11: ...tinguishes between an external program memory portion as mentioned above and up to 64 Kbyte external data memory accessed by a set of special instructions Bus Expansion Control The external bus interface of the SAB 80 C 515 80 C 535 consists of an 8 bit data bus port 0 a 16 bit address bus port 0 and port 2 and five control lines The address latch enable signal ALE is used to demultiplex address a...

Page 12: ...Semiconductor Group 12 Fundamental Structure Figure 2 1 Detailed Block Diagram ...

Page 13: ...rting of the power saving modes by software via special function register PCON Power Control Register protection against unintentional starting of the power saving modes These items are described in detail in section 7 6 2 1 2 Special Function Register PCON In the MYMOS version SAB 80515 80535 the SFR PCON address 87H contains only bit 7 SMOD In the ACMOS version SAB 80C515 80C535 there are additi...

Page 14: ...s digital inputs see chapter 7 4 Figure 2 2 Special Function Register PCON Address 87H Symbol Position Function SMOD PDS IDLS GF1 GF0 PDE IDLE PCON 7 PCON 6 PCON 5 PCON 4 PCON 3 PCON 2 PCON 1 PCON 0 When set the baud rate of the serial channel in mode 1 2 3 is doubled Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode Idle st...

Page 15: ...tor Please note that there is a difference between driving MYMOS and ACMOS components from external source How to drive each device is described in chapter 7 8 2 and in each data sheet 2 1 7 The VBB Pin The SAB 80515 80535 has an extra VBB pin connected to the device s substrate lt must be connected to VSS through a capacitor for proper operation of the A D converter The SAB 80C515 80C535 has no V...

Page 16: ...s the arithmetic operations add subtract multiply divide increment decrement BCD decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations of set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or it...

Page 17: ...ion of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register lf it is a two byte instruction the second is read during S4 of the same machine cycle lf it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored and the program counter is not incremented In any case execution is completed at the en...

Page 18: ...Semiconductor Group 18 Central Processing Unit Figure 3 1 Fetch Execute Sequence ...

Page 19: ... external memory If the EA pin is held low the SAB 80 C 515 fetches all instructions from the external program memory Since the SAB 80C535 80535 has no internal program memory pin EA must be tied low when using this device In either case the 16 bit program counter is the addressing mechanism Locations 03H through 93H in the program memory are used by interrupt service routines 4 2 Data Memory The ...

Page 20: ...ation These bits can be referred to in two ways both of which are acceptable for the ASM51 One way is to refer to their bit addresses i e 0 to 7FH The other way is by referencing to bytes 20H to 2FH Thus bits 0 to 7 can also be referred to as bits 20 0 to 20 7 and bits 08H and 0FH are the same as 21 0 to 21 7 and so on Each of the 16 bytes in this segment may also be addressed as a byte 3 Location...

Page 21: ...tten by other data and vice versa External Data Memory Figure 4 2 and 4 3 contain memory maps which illustrate the internal external data memory To address data memory external to the chip the MOVX instructions in combination with the 16 bit datapointer or an 8 bit general purpose register are used Refer to chapter 9 Instruction Set or 5 External Bus Interface for detailed descriptions of these op...

Page 22: ...Semiconductor Group 22 Memory Organization Figure 4 3 Mapping of the Lower Portion of the Internal Data Memory ...

Page 23: ...for data storage 4 4 Special Function Registers The Special Function Register SFR area has two important functions Firstly all CPU register except the program counter and the four register banks reside here The CPU registers are the arithmetic registers like A B PSW and pointers like SP DPH and DPL Secondly a number of registers constitute the interface between the CPU and all on chip peripherals ...

Page 24: ...ster 0 Interrupt priority register 0 Port 3 Interrupt enable register 1 Interrupt priority register 1 Interrupt request control register Compare capture enable register Compare capture register 1 low byte Compare capture register 1 high byte Compare capture register 2 low byte Compare capture register 2 high byte Compare capture register 3 low byte Compare capture register 3 high byte Timer 2 cont...

Page 25: ...efore data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in on chip RAM the stack pointer is initialized to 07H after a reset This causes the stack to begin at location 08H above register bank zero The SP can be read or written under software co...

Page 26: ... AN7 can only be used as inputs for the A D converter In the ACMCS versions these lines may also be used as digital inputs In this case they are addressed as an additional input port port 6 via special function register P6 0DBH Since port 6 has no internal latch the contents of SFR P6 only depends on the levels applied to the input lines For details about this port please refer to section 7 1 Para...

Page 27: ...as Data Address Bus When used for accessing external memory port 0 provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port 0 pins are not open drain outputs and do not require external pullup resistors During any a...

Page 28: ...is requires the ROM less versions SAB 80C535 80535 to have EA wired low to allow the lower 8 K program bytes to be fetched from external memory When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose I O The contents of the port 2 SFR however is not affected During external program memory fetches port...

Page 29: ...ernal memory The address byte is valid at the negative transition of ALE For that purpose ALE is activated twice every machine cycle This activation takes place even it the cycle involves no external fetch The only time no ALE pulse comes out is during an access to external data memory when RD WR signals are active The first ALE of the second cycle of a MOVX instruction is missing see figure 5 1b ...

Page 30: ...Semiconductor Group 30 External Bus Interface Figure 5 1 a and b External Program Memory Execution ...

Page 31: ...hine cycle in which RESET is low and is repeated every cycle until RESET goes high again During reset pins ALE and PSEN are configured as inputs and should not be stimulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins A pullup resistor is ...

Page 32: ...ort lines ports 1 through 5 output a one 1 In the MYMOS versions the analog input lines AN0 to AN7 can only be used as inputs In the ACMOS versions these lines may also be used as digital inputs In this case they are addressed as an additional input port port 6 via special function register P6 0DBH Since port 6 has no internal latch the contents of SFR P6 only depends on the levels applied to the ...

Page 33: ... DPTR 0000H TCON 00H TL0 TH0 00H TL2 TH2 00H IEN0 IEN1 00H IRCON 00H CCL1 CCH1 00H CCL3 CCH3 00H T2CON 00H ADCON 00X0 0000B DAPR 00H B 00H PC 0000H SP 07H PCON 000X 0000B TMOD 00H TL1 TH1 00H SCON 00H SBUF undefined IP0 X000 0000B IP1 XX00 0000B CCEN 00H CCL2 CCH2 00H CRCL CRCH 00H PSW 00H ADDAT 00H ACC 00H Watchdog 0000H ...

Page 34: ... RESET signal must be active for at least two machine cycles after this time the SAB 80 C 515 remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state ...

Page 35: ...f port 0 and 2 and the input buffers of port 0 are also used for accessing external memory In this application port 0 outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents see also chapter 7 1...

Page 36: ...ersion This could produce crosstalk to the analog signal 7 1 1 1 Digital I O Port Circuitry MYMOS ACMOS Figure 7 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the 6 I O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the ...

Page 37: ... the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current IIL or ITL For this reason these ports are sometimes called quasi bidirectional Figure 7 2 Basic Output Driver Circuit of Ports 1 through 5 In fact the pullups mentioned before and included in figure 7 2 are pullup arrangements as shown in figure 7 3 T...

Page 38: ...Semiconductor Group 38 On Chip Peripheral Components Figure 7 3 Output Driver Circuits of Ports 1 through 5 ...

Page 39: ...p FET p1 is of p channel type lt is activated for two oscillator periods S1P1 and S1P2 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a 0 The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type lt is always activated when a ...

Page 40: ...and provide a week 1 until the first 0 to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from outpout to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds IIL the pin can be force...

Page 41: ...y an internal control signal dependent on the input level at the EA pin and or the contents of the program counter lf the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the P2 SFR remains unchanged while the P0 SFR has 1 s written to it Being an address data bus port 0 uses a pullup FET as shown in figure 7 4 a When a 16 bit a...

Page 42: ...nput Ext interrupt 4 input compare 1 output capture 1 input Ext interrupt 5 input compare 2 output capture 2 input Ext interrupt 6 input compare 3 output capture 3 input Ext interrupt 2 input Timer 2 external reload trigger input System clock output Timer 2 external reload trigger input Serial port s receiver data input asynchronous or data input output synchronous Serial port s transmitter data o...

Page 43: ...between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pull down FET is on and the port pin is stuck at 0 This does not apply to ports 1 0 to 1 3 when operated in compare output mode refer to section 7 5 2 for details After reset all port latches contain ones 1 Figure 7 5...

Page 44: ...e cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 7 6 illustrates this port timing lt must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected ...

Page 45: ...pin the parameters ITL and IIL in the DC characteristics specify these currents Port 0 as well as the input only ports 6 of the ACMOS versions have floating inputs when used for digital input 7 1 4 3 Read Modify Write Feature of Ports 0 through 5 Some port reading instructions read the latch and others read the pin see figure 7 1 The instructions reading the latch rather than the pin read a value ...

Page 46: ...e port bit at the pin rather than the latch it will read the base voltage of the transistor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch However reading the latch rather than the...

Page 47: ...rate is fixed at 1 12 of the oscillator frequency Mode 1 8 bit UART variable baud rate 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB8 in special function register SCON The baud rate is variable Mode 2 9 bit UART fixed baud rate 11 bits are transmitted through TxD or received through RxD a star...

Page 48: ...ode fixed baud rate Serial mode 1 8 bit UART variable baud rate Serial mode 2 9 bit UART fixed baud rate Serial mode 3 9 bit UART variable baud rate SM2 Enables the multiprocessor communication feature in modes 2 and 3 In mode 2 or 3 and SM2 being set to 1 RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 and SM2 1 RI will not be activated if a valid stop bit has not been re...

Page 49: ...rating modes of the serial interface Table 7 3 Serial Interface Mode Selection Figure 7 8 Special Function Register SBUF Address 99H Receive and transmit buffer of serial interface Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register SM0 SM1 Mode Descriptions Baud Rate 0 0 0 Shift register fOSC 12 0 1 1 8 bit UART V...

Page 50: ... The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming After having received a complete message the slave sets SM2 again The slaves that were not addressed leave their SM2 set and go on about their business ignoring the incoming data bytes SM2 has no effect in mode 0 In mode 1 SM2 can be used to check the validity of the stop bit lf SM2 1 in mode 1 th...

Page 51: ... the internal baud rate generator for the serial interface To enable this feature bit BD bit 7 of special function register ADCON must be set see figure 7 10 This baud rate generator divides the oscillator frequency by 2500 Bit SMOD PCON 7 also can be used to enable a multiply by two prescaler see figure 7 9 At 12 MHz oscillator frequency the commonly used baud rates 4800 baud SMOD 0 and 9600 baud...

Page 52: ...se the baud rate is given by the formula One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001B and using the timer 1 interrupt for a 16 bit software reload Table 7 4 lists various commonly used baud rates and shows how they can be obtained from timer 1 Bit Function BD Baud rate enable When se...

Page 53: ... 5 summarizes the baud rate formulas for all usual configurations Figure 7 11 Generation of Baud Rates for Serial Interface Baud Rate fOSC MHz SMOD Timer 1 C T Mode Reload Value Mode 1 3 62 5 Kbaud 19 5 Kbaud 9 6 Kbaud 4 8 Kbaud 2 4 Kbaud 1 2 Kbaud 110 Baud 110 Baud 12 0 11 059 11 059 11 059 11 059 11 059 6 0 12 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 1 FFH FDH FDH FAH F4H E8H 72H FEEBH ...

Page 54: ...a simplified functional diagram of the serial port in mode 0 and associated timing Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse ...

Page 55: ...1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 in every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted one position to the left The value that comes in from the...

Page 56: ...tion is detected the divide by 16 counter is immediately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollover with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16 counter states At the 7th 8th and 9th counter state of each bit time the bit detector samples the value of RxD The value accepte...

Page 57: ...nal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter thus the bit times are synchronized to the divide by 16 counter and not to the write to SBUF signal The transmission begins with the activation of SEND w...

Page 58: ... at the leftmost position in the shift register which is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 either SM2 0 or the received 9th data bit 1 lf either one of these two con...

Page 59: ...Semiconductor Group 59 On Chip Peripheral Components Figure 7 16 a Functional Diagram Serial Interface Mode 0 ...

Page 60: ...Semiconductor Group 60 On Chip Peripheral Components Figure 7 16 b Timing Diagram Serial Interface Mode 0 ...

Page 61: ...Semiconductor Group 61 On Chip Peripheral Components Figure 7 17 a Functional Diagram Serial Interface Mode 1 ...

Page 62: ...Semiconductor Group 62 On Chip Peripheral Components Figure 7 17 b Timing Diagram Serial Interface Mode 1 ...

Page 63: ...Semiconductor Group 63 On Chip Peripheral Components Figure 7 18 a Functional Diagram Serial Interface Modes 2 and 3 ...

Page 64: ...Semiconductor Group 64 On Chip Peripheral Components Figure 7 18 b Timing Diagram Serial Interface Modes 2 and 3 ...

Page 65: ...the register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin T0 or T1 alternate functions of P3 4 and P3 5 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 ...

Page 66: ...timer 0 TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer 0 If not explicitly noted this applies also to timer 1 Bit Function TR0 Timer 0 run control bit Set cleared by software to turn timer counter 0 ON OFF TF0 Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run co...

Page 67: ... from Tx input pin Cleared for timer operation input from internal system clock M1 M0 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer 0 TL0 is an 8 bit timer counter ...

Page 68: ...R0 1 and either GATE 0 or INT0 1 setting GATE 1 allows the timer to be controlled by external input INT0 to facilitate pulse width measurements TR0 is a control bit in the special function register TCON GATE is in TMOD The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TL0 The upper 3 bits of TL0 are indeterminate and should be ignored Setting the run flag TR0 does not clear...

Page 69: ...pheral Components 7 3 2 Mode 1 Mode 1 is the same as mode 0 except that the timer register is run with all 16 bits Mode 1 is shown in figure 7 22 Figure 7 22 Timer Counter 0 Mode 1 16 Bit Timer Counter The same applies to timer counter 1 ...

Page 70: ... bit counter TL0 with automatic reload as shown in figure 7 23 Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents of TH0 which is preset by software The reload leaves TH0 unchanged Figure 7 23 Timer Counter 0 Mode 2 8 Bit Timer Counter with Auto Reload The same applies to timer counter 1 ...

Page 71: ...TE TR0 INT0 and TF0 TH0 is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus TH0 now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channe...

Page 72: ...ime Internal start of conversion trigger Interrupt request generation after each conversion For the conversion the method of successive approximation via capacitor array is used The externally applied reference voltage range has to be held on a fixed value within the specifications see section A D Converter Characteristics in the data sheet The internal reference voltages can be varied to reduce t...

Page 73: ...Semiconductor Group 73 On Chip Peripheral Components Figure 7 25 A D Converter Block Diagram ...

Page 74: ...on of the previous one The busy flag BSY ADCON 4 is automatically set when a conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect There is also an interrupt request flag IADC IRCON 0 that is set when a conversion is completed See section 8 for more details about the interrupt structure Bit Function MX0 MX1 MX2 Select ...

Page 75: ... additional general purpose register Figure 7 28 Special Function Register ADDAT Address 0D9H This register contains the 8 bit conversion result 7 4 1 2 Start of Conversion An internal start of conversion is triggered by a write to DAPR instruction The start procedure itself is independent of the value which is written to DAPR However the value in DAPR determines which internal reference voltages ...

Page 76: ...rammable D A converter which provides the voltages VIntARFF and VIntAGND for the A D converter itself The SFR DAPR see figure 7 29 is provided for programming the internal reference voltages VIntAREF and VlntAGND For this purpose the internal reference voltages can be programmed in steps of 1 16 of the external reference voltages VAREF VAGND by four bits each in register DAPR Bits 0 to 3 specify V...

Page 77: ...0 V and VAREF 5 V with respect to VSS and VCC are applied then the following internal reference voltages VIntAGND and VIntAREF shown in table 7 7 can be adjusted via the special function register DAPR Figure 7 29 Special Function Register DAPR Address DAH D A converter program register Each 4 bit nibble is used to program the internal reference voltages Write access to DAPR starts conversion DAPR ...

Page 78: ...nalog input voltage by starting a second conversion with a compressed internal reference voltage range close to the previously measured analog value Figures 7 30 and 7 31 illustrate these applications Step DAPR 3 0 DAPR 7 4 VIntAGND VIntAREF 0 0000 0 0 5 0 1 0001 0 3125 2 0010 0 625 3 0011 0 9375 4 0100 1 25 1 25 5 0101 1 5625 1 5625 6 0110 1 875 1 875 7 0111 2 1875 2 1875 8 1000 2 5 2 5 9 1001 2 ...

Page 79: ...uctor Group 79 On Chip Peripheral Components Figure 7 30 Adjusting the Internal Reference Voltages within Range of the External Analog Input Voltages Figure 7 31 Increasing the Resolution by a Second Conversion ...

Page 80: ...started by writing into special function register DAPR A write to DAPR will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the busy flag BSY will be set The conversion procedure is divided into three parts Load time tL During this time the analog input capacitance CI see data sheet must be loaded to the analog input voltag...

Page 81: ...et some cycles before the result is written to ADDAT The flag IADC is set before the result is available in ADDAT because the shortest possible interrupt latency time is taken into account in order to ensure optimal performance Thus the converted result appears at the same time in ADDAT when the first instruction of the interrupt service routine is executed Similar considerations apply to the timi...

Page 82: ...ase AC and stepper motor control frequency generation digital to analog conversion process control Please note that this timer is not equivalent to timer 2 of the SAB 80 C 52 see section 7 5 1 Timer 2 in combination with the compare capture reload registers allows the following modes Compare up to 4 PWM signals with 65535 steps at maximum and 1 µsec resolution Capture up to 4 high speed inputs wit...

Page 83: ...Semiconductor Group 83 On Chip Peripheral Components Figure 7 33 a Timer 2 Block Diagram ...

Page 84: ...tput O Function P1 7 T2 I O External count or gate input to timer 2 P1 5 T2EX I O External reload trigger input P1 3 INT6 CC3 I O Comp output capture input for CC register 3 P1 2 INT5 CC2 I O Comp output capture input for CC register 2 P1 1 INT4 CC1 I O Comp output capture input for CC register 1 P1 0 INT3 CC0 I O Comp output capture input for CRC register ...

Page 85: ...prescaler gates 1 24 of the oscillator frequency to the timer Gated Timer Mode In gated timer function the external input pin T2 P1 7 functions as a gate to the input of timer 2 lf T2 is high the internal clock input is gated to the timer T2 0 stops the counting procedure This will facilitate pulse width measurements The external gate signal is sampled once every machine cycle for the exact port t...

Page 86: ...rate a timer overflow interrupt the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt for EXF2 see below Both request flags cause the program to branch to the same vector address The input clock to timer 2 is selected by bits T2I0 T2I1 and T2PS as listed ...

Page 87: ...ad upon falling edge at pin T2EX P1 5 T2CM Compare mode bit for registers CRC CC1 through CC3 When set compare mode 1 is selected T2CM 0 selects compare mode 0 I3FR External interrupt 3 falling rising edge flag also used for capture function in combination with register CRC see section 7 5 3 If set capture to register to CRC if enabled will occur on a positive transition at pin P1 0 INT3 CC0 If I3...

Page 88: ... note that the compare interrupt CC0 can be programmed to be negative or positive transition activated The internal compare signal not the output signal at the port pin is active as long as the timer 2 contents is equal to the one of the appropriate compare registers and it has a rising and a falling edge Thus when using the CRC register it can be selected whether an interrupt should be caused whe...

Page 89: ...conductor Group 89 On Chip Peripheral Components Figure 7 35 Port Latch in Compare Mode 0 Figure 7 36 Timer 2 with Registers CCx in Compare Mode 0 CCx stands for CRC CC1 to CC3 IEXx stands for IEX3 to IEX6 ...

Page 90: ... to the reload value limiting the lower end of the modulation range or it may occur at the end of a timer period In a timer 2 CCx register configuration in compare mode 0 this spike is divided into two halves one at the beginning when the contents of the compare register is equal to the reload value of the timer the other half when the compare register is equal to the maximum value of the timer re...

Page 91: ...te with reasonable numbers a reduction of the resolution to 8 bit is used Otherwise for the maximum resolution of 16 bit the modulation range would be so severely limited that it would be negligible Example Timer 2 in auto reload mode contents of reload register CRC 0FF00H This leads to a variation of the duty cycle from 0 195 to 99 805 for a timer 2 CCx register configuration when 8 of 16 bits ar...

Page 92: ... Figure 7 39 shows a functional diagram of a timer compare register port latch configuration in compare mode 1 In this function the port latch consists of two separate latches The upper latch which acts as a shadow latch can be written under software control but its value will only be transferred to the output latch and thus to the port pin in response to a compare match Note that the double latch...

Page 93: ...Semiconductor Group 93 On Chip Peripheral Components Figure 7 39 Timer 2 with Registers CCx in Compare Mode 1 CCx stands for CRC CC1 to CC3 IEXx stands for IEX3 to IEX6 ...

Page 94: ...nput is directly connected to the internal compare signal thus providing a compare interrupt Bit Function COCAH0 COCAL0 0 0 0 1 1 0 1 1 Compare capture mode for CRC register Compare capture disabled Capture on falling rising edge at pin P1 0 INT3 CC0 Compare enabled Capture on write operation into register CRCL COCAH1 COCAL1 0 0 0 1 1 0 1 1 Compare capture mode for CC register 1 Compare capture di...

Page 95: ...t event This in turn is supposed to happen after a sufficient space of time Please note two special cases where a program using compare interrupts could show a surprising behavior The first configuration has already been mentioned in the description of compare mode 1 The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock In t...

Page 96: ...y In mode 0 the external event causing a capture is for CC registers 1 to 3 a positive transition at pins CC1 to CC3 of port 1 for the CRC register a positive or negative transition at the corresponding pin depending on the status of the bit I3FR in SFR T2CON lf the edge flag is cleared a capture occurs in response to a negative transition if the edge flag is set a capture occurs in response to a ...

Page 97: ...tion of the compare capture registers 1 to 3 The two capture modes can be established individually for each capture register by bits in SFR CCEN compare capture enable register That means in contrast to the compare modes it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register The bit positions and functions of CCEN are listed in figure 7 40 Figure 7 ...

Page 98: ...nt in the following sections There are numerous applications which require high system security and at the same time reliability in electrically noisy environments In such applications unintentional entering of the power saving modes must be absolutely avoided A power saving mode would reduce the controller s perfomance in case of idle mode or even stop each operation in case of power down mode Th...

Page 99: ...CC VPD the current for the 40 bytes is drawn from VPD The addresses of these backup powered RAM locations range from 88 to 127 58H to 7FH The current drawn from the backup power supply is typically 1 mA max 3 mA To utilize this feature the user s system upon detecting an imminent power failure would interrupt the processor in some manner to transfer relevant data to the 40 byte on chip RAM and ena...

Page 100: ...is not possible The instruction sequences used for entering these modes will not affect the normal operation of the device PE 0 logic low level All power saving modes can be activated as described in the following sections When left unconnected the pin PE is pulled to high level by a weak internal pullup This is done to provide system protection by default In addition to the hardware enable disabl...

Page 101: ...re 7 44 shows the special function register PCON This double instruction sequence is implemented to minimize the chance of unintentionall entering the power down mode which could possibly freeze the chip s activity in an undesired status Note that PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is composed of byte handling instructions The fo...

Page 102: ...teristics in the data sheet Thus the user has to make sure that the right peripheral continues to run or is stopped respectively during idle Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle Normally the port pins hold the logical state they had at the time idle was activ...

Page 103: ... must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS will not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after having been set lt one of these register bits is read the value shown is zero 0 Figure 7 44 shows special function register PCON This double instruction sequence is implemented to minimize the chance of uninte...

Page 104: ...er possibility of terminating the idle mode is a hardware reset Since the oscillator is still running the hardware reset is held active for only two machine cycles for a complete reset Figure 7 44 Special Function Register PCON Address 87H of the SAB 80C515 80C535 Bit Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down...

Page 105: ...For this reason setting SWDT bit has to be a one cycle instruction e g SETB SWDT This double instruction clearing of the watchdog timer was implemented to minimize the chance of unintentionally clearing the watchdog To prevent the watchdog from overflowing it must be cleared periodically Starting the watchdog timer by setting only bit SWDT does not reload the WDTREL register to the watchdog timer ...

Page 106: ...g WDT a watchdog timer refresh is performed Bit SWDT is reset by hardware two processor cycles after it has been set Bit Function WDTS Watchdog timer status flag Set by hardware when the watchdog timer was started Can be read by software These bits are not used by the watchdog timer 0BFH 0BEH 0BDH 0BCH 0BBH 0BAH 0B9H 0B8H EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC 0B8H IEN1 These bits are not used by the...

Page 107: ... crystal controlled positive reactance oscillator a more detailed schematic is given in figure 7 49 and 7 51 lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 30 pF can be used as single capacitance at any frequency together with a good qual...

Page 108: ...rnal clock source the external clock signal is to be applied to XTAL2 A pullup resistor is recommended to increase the noise margin but is optional if the output high level of the driving gate meets the VIH1 specification of XTAL2 XTAL1 has to be connected to ground see figure 7 50 Figure 7 49 On Chip Oscillator Circuitry Figure 7 50 External Clock Source ...

Page 109: ...m an external clock source the external clock signal is to be applied to XTAL2 as shown in figure 7 52 A pullup resistor is recommended but is optional if the output high level of the driving gate corresponds to the VIH1 specification of XTAL2 XTAL1 has to be left unconnected Figure 7 51 On Chip Oscillator Circuitry Figure 7 52 External Clock Source ...

Page 110: ...h is also the default after reset Figure 7 53 Special Function Register ADCON Address 0D8H The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states Thus the duty cycle of the clock signal is 1 6 Associated with a MOVX instruction the system clock coincides with the last state S3 in which a RD or WR signal is active A timing diagram of the system clock ou...

Page 111: ...Semiconductor Group 111 On Chip Peripheral Components Figure 7 54 Timing Diagram System Clock Output ...

Page 112: ...er e g TCON IRCON SCON Provided that the peripheral or external source meets the condition for an interrupt the dedicated request flag is set whether an interrupt is enabled or not For example each timer 0 overflow sets the corresponding request flag TF0 lf it is already set it retains a one 1 But the interrupt is not necessarily serviced Now each interrupt requested by the corresponding flag can ...

Page 113: ...Semiconductor Group 113 Interrupt System Figure 8 1 a Interrupt Structure of the SAB 80 C 515 80 C 535 ...

Page 114: ...Semiconductor Group 114 Interrupt System Figure 8 1 b Interrupt Structure of the SAB 80 C 515 80 C 535 cont d ...

Page 115: ...s the timer 1 overflow interrupt If ET1 0 the timer 1 interrupt is disabled ES Enables or disables the serial channel interrupt If ES 0 the serial channel interrupt is disabled ET2 Enables or disables the timer 2 overflow or external reload interrupt If ET2 0 the timer 2 interrupt is disabled EAL Enables or disables all interrupts If EAL 0 no interrupt will be acknowledged If EAL 1 each interrupt ...

Page 116: ...er 0 in mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored too Bit Function EADC Enables or disables the A D converter interrupt If EADC 0 the A D converter interrupt is disabled EX2 Enables or disables external interrupt 2 capture compare interrupt 4 If EX2 0 external interrupt 2 is disabled EX3 Enables or ...

Page 117: ...t is if an interrupt is generated in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine with respect to the minimal interrupt response time lf continuous conversions are established IADC is set once during each conversion lf an A D converter interrupt is generated flag IADC will have to be cleared by software Bit Function IT0 Interrupt 0 type ...

Page 118: ...upts 4 INT4 5 INT5 6 INT6 are positive transition activated The flags that actually generate these interrupts are bits IEX4 IEX5 and IEX6 in register IRCON see figure 8 6 In addition these flags will be set if a compare event occurs at the corresponding output pin P1 1 INT4 CC1 P1 2 INT5 CC2 and P1 3 INT6 CC3 regardless of the compare mode established and the transition at the respective pin When ...

Page 119: ...terrupt processed IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 2 INT5 CC2 Cleared when interrupt processed IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at pin 1 3 INT6 CC3 Cleared when interrupt processed TF2 Timer 2 overflow f...

Page 120: ...ures 8 2 and 8 3 Note that IEN0 contains also a global disable bit EAL which disables all interrupts at once Also note that in the SAB 8051 the interrupt priority register IP is located at address 0B8H in the SAB 80 C 515 80 C 535 this location is occupied by register IEN1 8 2 Priority Level Structure As already mentioned above all interrupt sources are combined as pairs table 8 1 lists the struct...

Page 121: ...t is serviced first The pairs are serviced from top to bottom of the table Figure 8 7 Special Function Registers IP0 and IP1 Address 0A9H and 0B9H Corresponding bit locations in both registers are used to set the interrupt priority level of an interrupt pair Bit Function IP1 x IP0 x 0 0 Set priority level 0 lowest 0 1 Set priority level 1 1 0 Set priority level 2 1 1 Set priority level 3 highest B...

Page 122: ... of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IEN0 IEN1 IEN2 or IP0 and IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is comp...

Page 123: ...f an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 8 9 then in accordance with the above rules it will be vectored too during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In so...

Page 124: ...nt interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged Interrupt Request Flags Interrupt Vector Address Interrupt Source IE0 0003H External interrupt 0 TF0 000B...

Page 125: ...ative or positive transition activated by setting or clearing bit I2FR or I3FR in register T2CON see figure 8 5 lf IxFR 0 x 2 or 3 external interrupt x is negative transition activated lf IxFR 1 external interrupt is triggered by a positive transition The external interrupts 4 5 and 6 are activated by a positive transition The external timer 2 reload trigger interrupt request flag EXF2 will be act...

Page 126: ...ce routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions lf an interrupt of equal or higher priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine lf the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cyc...

Page 127: ...bler or high level languages 9 1 Addressing Modes The SAB 80 C 515 80 C 535 uses five addressing modes register direct immediate register indirect base register plus index register indirect Table 9 1 summarizes the memory spaces which may be accessed by each of the addressing modes Register Addressing Register addressing accesses the eight working registers R0 R7 of the selected register bank The ...

Page 128: ...side anywhere in the internal RAM Base Register plus Index Register Addressing Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register DPTR or PC and index register ACC This mode facilitates look up table accesses Boolean Processor The Boolean processor is a bit processor integr...

Page 129: ...ally AND ed or OR ed with the contents of the carry flag The result is returned to the carry register 9 2 Introduction to the Instruction Set The instruction set is divided into four functional groups data transfer arithmetic logic control transfer 9 2 1 Data Transfer Data operations are divided into three classes general purpose accumulator specific address object None of these operations affects...

Page 130: ... table pointed to by the base register DPTR or PC The byte operand accessed is transferred to the accumulator Address Object Transfer MOV DPTR data loads 16 bits of immediate data into a pair of destination registers DPH and DPL 9 2 2 Arithmetic The SAB 80 C 515 80 C 535 has four basic mathematical operations Only 8 bit operations using unsigned arithmetic are supported directly The overflow flag ...

Page 131: ...ta in registers A and B and sets OV otherwise OV is cleared CY is cleared AC remains unaffected Flags Unless otherwise stated in the previous descriptions the flags of PSW are affected as follows CY is set if the operation causes a carry to or a borrow from the resulting high order bit otherwise CY is cleared AC is set if the operation results in a carry from the low order four bits of the result ...

Page 132: ...last bit rotated out SWAP rotates A left four places to exchange bits 3 through 0 with bits 7 through 4 Two Operand Operations ANL performs bitwise logical AND of two operands for both bit and byte operands and returns the result to the location of the first operand ORL performs bitwise logical OR of two source operands for both bit and byte operands and returns the result to the location of the f...

Page 133: ...e offset 0 255 to the address in the DPTR register Thus the effective destination for a jump can be anywhere in the program memory space Conditional Jumps Conditional jumps perform a jump contingent upon a specific condition The destination will be within a 256 byte range centered about the starting address of the next instruction 128 to 127 JZ performs a jump if the accumulator is zero JNZ perfor...

Page 134: ...ing and a symbolic description or restatement of the function is also provided Note Only the carry auxiliary carry and overflow flags are discussed The parity bit is computed after every instruction cycle that alters the accumulator Similarily instructions which alter directly addressed registers could affect the other status flags if the instruction is applied to the PSW Status flags can also be ...

Page 135: ...8 software flags any bitaddressable l O pin control or status bit A Accumulator Notes on Program Addressing Modes addr16 Destination address for LCALL and LJMP may be anywhere within the 64 Kbyte program memory address space addr11 Destination address for ACALL and AJMP will be within the same 2 Kbyte page of program memory as the first byte of the following instruction rel SJMP and all conditiona...

Page 136: ...the incremented PC op code bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL No flags are affected Example Initially SP equals 07H The label SUBRTN is at program memory location 0345H After executing the instruction ACALL SUBRTN at location 0123H SP will contain ...

Page 137: ...ot out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 0C3H 11000011B and register 0 holds 0AAH 10101010B The instruction ADD A R0 will leav...

Page 138: ...Semiconductor Group 138 Instruction Set ADD A Ri Operation ADD A A Ri Bytes 1 Cycles 1 ADD A data Operation ADD A A data Bytes 2 Cycles 1 Encoding 0 0 1 0 0 1 1 i Encoding 0 0 1 0 0 1 0 0 immediate data ...

Page 139: ...of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 0C3H 11000011B and register 0 holds 0AAH 10101010B with the carry flag ...

Page 140: ...conductor Group 140 Instruction Set ADDC A Ri Operation ADDC A A C Ri Bytes 1 Cycles 1 ADDC A data Operation ADDC A A C data Bytes 2 Cycles 1 Encoding 0 0 1 1 0 1 1 i Encoding 0 0 1 1 0 1 0 0 immediate data ...

Page 141: ...PC twice op code bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP Example The label JMPADR is at program memory location 0123H The instruction AJMP JMPADR is at location 0345H and will load the PC with 0123H Operation AJM P PC PC 2 PC10 0 page address Bytes 2 Cycles 2 Enc...

Page 142: ...uction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3H 11000011B and register 0 holds 0AAH 10101010B then the instruction ANL A R0 will leave 81H 10000001B in the accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in ...

Page 143: ... A Ri Operation ANL A A Ri Bytes 1 Cycles 1 ANL A data Operation ANL A A data Bytes 2 Cycles 1 ANL direct A Operation ANL direct direct A Bytes 2 Cycles 1 Encoding 0 1 0 1 0 1 0 1 direct address Encoding 0 1 0 1 0 1 1 i Encoding 0 1 0 1 0 1 0 0 immediate data Encoding 0 1 0 1 0 1 0 1 direct address ...

Page 144: ...Semiconductor Group 144 Instruction Set ANL direct data Operation ANL direct direct data Bytes 3 Cycles 2 Encoding 0 1 0 1 0 0 1 1 direct address immediate data ...

Page 145: ...dressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct bit addressing is allowed for the source operand Example Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV C P1 0 Load carry with input pin state ANL C ACC 7 AND carry with accumulator bit 7 ANL C OV AND with inverse of overflow flag ANL C bit Operation ANL C C bit ...

Page 146: ...nations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant Example The accumulator contains 34H Register 7 contains 56H The first instruction in the sequence CJNE R7 60H NOT_EQ R7 60H NOT_EQ JC REQ_LOW If R7 60H R7 60H sets the carry flag and branches to the instruction at l...

Page 147: ...el Operation PC PC 3 if A data then PC PC relative offset if A data then C 1 else C 0 Bytes 3 Cycles 2 CJNE RN data rel Operation PC PC 3 if Rn data then PC PC relative offset if Rn data then C 1 else C 0 Bytes 3 Cycles 2 Encoding 1 0 1 1 0 1 0 1 direct address rel address Encoding 1 0 1 1 0 1 0 0 immediate data rel address Encoding 1 0 1 1 1 r r r immediate data rel address ...

Page 148: ...conductor Group 148 Instruction Set CJNE Ri data rel Operation PC PC 3 if Ri data then PC PC relative offset if Ri data then C 1 else C 0 Bytes 3 Cycles 2 Encoding 1 0 1 1 0 1 1 i immediate data rel address ...

Page 149: ...mulator Description The accumulator is cleared all bits set to zero No flags are affected Example The accumulator contains 5CH 01011100B The instruction CLR A will leave the accumulator set to 00H 00000000B Operation CLR A 0 Bytes 1 Cycles 1 Encoding 1 1 1 0 0 1 0 0 ...

Page 150: ...cted CLR can operate on the carry flag or any directly addressable bit Example Port 1 has previously been written with 5DH 01011101B The instruction CLR P1 2 will leave the port set to 59H 01011001B CLR C Operation CLR C 0 Bytes 1 Cycles 1 CLR bit Operation CLR bit 0 Bytes 2 Cycles 1 Encoding 1 1 0 0 0 0 1 1 Encoding 1 1 0 0 0 0 1 0 bit address ...

Page 151: ...r is logically complemented one s complement Bits which previously contained a one are changed to zero and vice versa No flags are affected Example The accumulator contains 5CH 01011100B The instruction CPL A will leave the accumulator set to 0A3H 10100011 B Operation CPL A A Bytes 1 Cycles 1 Encoding 1 1 1 1 0 1 0 0 ...

Page 152: ...ddressable bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Example Port 1 has previously been written with 5DH 01011101B The instruction sequence CPL P1 1 CPL P1 2 will leave the port set to 5BH 01011011B CPL C Operation CPL C C Bytes 1 Cycles 1 CPL bit Operation CPL bit bit Bytes 2 Cycles ...

Page 153: ...inal two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD n...

Page 154: ...ng the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 29H in the accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 Operation DA contents of accumulator are BCD if A3 0 9 AC 1 then A3 0 A3 0 6 and if A7 4 9 C 1 then A7 4 A7 4 6 Bytes 1 Cycles 1 Encoding 1 1 0 1 0 1 0 0 ...

Page 155: ...used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Register 0 contains 7FH 01111111B Internal RAM locations 7EH and 7FH contain 00H and 40H respectively The instruction sequence DEC R0 DEC R0 DEC R0 will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH DEC A Operation DEC A ...

Page 156: ...iconductor Group 156 Instruction Set DEC direct Operation DEC direct direct 1 Bytes 2 Cycles 1 DEC Ri Operation DEC Ri Ri 1 Bytes 1 Cycles 1 Encoding 0 0 0 1 0 1 0 1 direct address Encoding 0 0 0 1 0 1 1 i ...

Page 157: ...ill be cleared Exception If B had originally contained 00H the values returned in the accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case Example The accumulator contains 251 0FBH or 11111011B and B contains 18 12H or 00010010B The instruction DIV AB will leave 13 in the accumulator 0DH or 00001101 B and the value 17 11H or 00010001B...

Page 158: ... value used as the original port data will be read from the output data latch not the input pins Example Internal RAM locations 40H 50H and 60H contain the values 01H 70H and 15H respectively The instruction sequence DJNZ 40H LABEL_1 DJNZ 50H LABEL_2 DJNZ 60H LABEL_3 will cause a jump to the instruction at label LABEL_2 with the values 00H 6FH and 15H in the three RAM locations The first jump was ...

Page 159: ...NZ PC PC 2 Rn Rn 1 if Rn 0 or Rn 0 then PC PC rel Bytes 2 Cycles 2 DJNZ direct rel Operation DJNZ PC PC 2 direct direct 1 if direct 0 or direct 0 then PC PC rel Bytes 3 Cycles 2 Encoding 1 1 0 1 1 r r r rel address Encoding 1 1 0 1 0 1 0 1 direct address rel address ...

Page 160: ... output port the value used as the original port data will be read from the output data latch not the input pins Example Register 0 contains 7EH 01111110B Internal RAM locations 7EH and 7FH contain 0FFH and 40H respectively The instruction sequence INC R0 INC R0 INC R0 will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding respectively 00H and 41H INC A Operation INC A A 1...

Page 161: ...iconductor Group 161 Instruction Set INC direct Operation INC direct direct 1 Bytes 2 Cycles 1 INC Ri Operation INC Ri Ri 1 Bytes 1 Cycles 1 Encoding 0 0 0 0 0 1 0 1 direct address Encoding 0 0 0 0 0 1 1 i ...

Page 162: ...ow order byte of the data pointer DPL from 0FFH to 00H will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Example Registers DPH and DPL contain 12H and 0FEH respectively The instruction sequence INC DPTR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H Operation INC DPTR DPTR 1 Bytes 1 Cycles 2 Encoding 1 0 1 0 0 0 1 1 ...

Page 163: ...hird instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected Example The data present at input port 1 is 11001010B The accumulator holds 56 01010110B The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 Operation JB PC PC 3 if bit ...

Page 164: ...ing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin Example The accumulator holds 56H 01010110B The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified ...

Page 165: ...y adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice No flags are affected Example The carry flag is cleared The instruction sequence JC LABEL1 CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 Operation JC PC PC 2 if C 1 then PC PC rel Bytes 2 Cycles 2 Encoding ...

Page 166: ...der bits Neither the accumulator nor the data pointer is altered No flags are affected Example An even number from 0 to 6 is in the accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR JMP_TBL AJMP LABEL0 AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator equals 04H when starting this seq...

Page 167: ...third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected Example The data present at input port 1 is 11001010B The accumulator holds 56H 01010110B The instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 Operation JNB PC PC 3 ...

Page 168: ...ed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified Example The carry flag is set The instruction sequence JNC LABEL1 CPL C JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2 Operation JNC PC PC 2 if C 0 then PC PC rel ...

Page 169: ... is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected Example The accumulator originally holds 00H The instruction sequence JNZ LABEL1 INC A JNZ LABEL2 will set the accumulator to 01H and continue at label LABEL2 Operation JNZ PC PC 2 if A 0 then PC PC rel Bytes 2 Cycles...

Page 170: ...relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected Example The accumulator originally contains 01H The instruction sequence JZ LABEL1 DEC A JZ LABEL2 will change the accumulator to 00H and cause program execution to continue at the instruction identified by the label LABEL2 Operation JZ PC PC 2 if A 0...

Page 171: ...ytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space No flags are affected Example Initially the stack pointer equals 07H The label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the stack pointer...

Page 172: ... the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected Example The label JMPADR is assigned to the instruction at program memory location 1234H The instruction LJMP JMPADR at location 0123H will load the program counter with 1234H Operation LJMP PC addr15 0 Bytes 3 Cycles 2 Encoding 0 0 0 0 0 0 1 0 addr15...

Page 173: ...ed Example Internal RAM location 30H holds 40H The value of RAM location 40H is 10H The data present at input port 1 is 11001010B 0CAH MOV R0 30H R0 30H MOV A R0 A 40H MOV R1 A R1 40H MOV B R1 B 10H MOV R1 P1 RAM 40H 0CAH MOV P2 P1 P2 0CAH leaves the value 30H in register 0 40H in both the accumulator and register 1 10H in register B and 0CAH 11001010B both in RAM location 40H and output on port 2...

Page 174: ...s 1 MOV A data Operation MOV A data Bytes 2 Cycles 1 MOV Rn A Operation MOV Rn A Bytes 1 Cycles 1 MOV Rn direct Operation MOV Rn direct Bytes 2 Cycles 2 Encoding 1 1 1 0 0 1 1 i Encoding 0 1 1 1 0 1 0 0 immediate data Encoding 1 1 1 1 1 r r r Encoding 1 0 1 0 1 r r r direct address ...

Page 175: ...V direct A Bytes 2 Cycles 1 MOV direct Rn Operation MOV direct Rn Bytes 2 Cycles 2 MOV direct direct Operation MOV direct direct Bytes 3 Cycles 2 Encoding 0 1 1 1 1 r r r immediate data Encoding 1 1 1 1 0 1 0 1 direct address Encoding 1 0 0 0 1 r r r direct address Encoding 1 0 0 0 0 1 0 1 dir addr src dir addr dest ...

Page 176: ...data Operation MOV direct data Bytes 3 Cycles 2 MOV Ri A Operation MOV Ri A Bytes 1 Cycles 1 MOV Ri direct Ooeration MOV Ri direct Bytes 2 Cycles 2 Encoding 1 0 0 0 0 1 1 i direct address Encoding 0 1 1 1 0 1 0 1 direct address immediate data Encoding 1 1 1 1 0 1 1 i Encoding 1 0 1 0 0 1 1 i direct address ...

Page 177: ...Semiconductor Group 177 Instruction Set MOV Ri data Operation MOV Ri data Bytes 2 Cycles 1 Encoding 0 1 1 1 0 1 1 i immediate data ...

Page 178: ...rectly addressable bit No other register or flag is affected Example The carry flag is originally set The data present at input port 3 is 11000101B The data previously written to output port 1 is 35H 00110101B MOV P1 3 C MOV C P3 3 MOV P1 2 C will leave the carry cleared and change port 1 to 39H 00111001 B MOV C bit Operation MOV C bit Bytes 2 Cycles 1 MOV bit C Operation MOV bit C Bytes 2 Cycles ...

Page 179: ...he instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once Example The instruction MOV DPTR 1234H will load the value 1234H into the data pointer DPH will hold 12H and DPL will hold 34H Operation MOV DPTR data15 0 DPH DPL data15 8 data7 0 Bytes 3 Cycles 2 Encoding...

Page 180: ... performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected Example A value between 0 and 3 is in the accumulator The following instructions will translate the value in the accumulator to one of four values defined by the DB define byte directive REL_PC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the a...

Page 181: ...Semiconductor Group 181 Instruction Set MOVC A A PC Operation MOVC PC PC 1 A A PC Bytes 1 Cycles 2 Encoding 1 0 0 0 0 0 1 1 ...

Page 182: ...dress bits the contents of DPH while P0 multiplexes the low order eight bits DPL with data The P2 special function register retains its previous contents while the P2 output buffers are emitting the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64 Kbyte since no additional instructions are needed to set up the output ports It is possible in some...

Page 183: ...Ri Bytes 1 Cycles 2 MOVX A DPTR Operation MOVX A DPTR Bytes 1 Cycles 2 MOVX Ri A Operation MOVX Ri A Bytes 1 Cycles 2 MOVX DPTR A Operation MOVX DPTR A Bytes 1 Cycles 2 Encoding 1 1 1 0 0 0 1 i Encoding 1 1 1 0 0 0 0 0 Encoding 1 1 1 1 0 0 1 i Encoding 1 1 1 1 0 0 0 0 ...

Page 184: ... in B If the product is greater than 255 0FFH the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the accumulator holds the value 80 50H Register B holds the value 160 0A0H The instruction MUL AB will give the product 12 800 3200H so B is changed to 32H 00110010B and the accumulator is cleared The overflow flag is set carry is cleared Operation MUL ...

Page 185: ...d Example It is desired to produce a low going output pulse on bit 7 of port 2 lasting exactly 5 cycles A simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR P2 7 NOP NOP NOP NOP SETB P2 7 Operation NOP Bytes 1 Cycles 1 Encoding 0 0 0 0 0 0 0 0 ...

Page 186: ...is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3H 11000011B and R0 holds 55H 01010101B then the instruction ORL A R0 will leave the accumulator holding the value 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any ...

Page 187: ... A Ri Operation ORL A A Ri Bytes 1 Cycles 1 ORL A data Operation ORL A A data Bytes 2 Cycles 1 ORL direct A Operation ORL direct direct A Bytes 2 Cycles 1 Encoding 0 1 0 0 0 1 0 1 direct address Encoding 0 1 0 0 0 1 1 i Encoding 0 1 0 0 0 1 0 0 immediate data Encoding 0 1 0 0 0 0 1 0 direct address ...

Page 188: ...Semiconductor Group 188 Instruction Set ORL direct data Operation ORL direct direct data Bytes 3 Cycles 2 Encoding 0 1 0 0 0 0 1 1 direct address immediate data ...

Page 189: ...ement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Example Set the carry flag if and only if P1 0 1 ACC 7 1 or OV 0 MOV C P1 0 Load carry with input pin P1 0 ORL C ACC 7 OR carry with the accumulator bit 7 ORL C OV OR carry with the inverse of OV ORL C bit Operation ORL C C bit Bytes 2 Cycles 2 ORL C bit Operation ORL C C bi...

Page 190: ...riginally contains the value 32H and internal RAM locations 30H through 32H contain the values 20H 23H and 01H respectively The instruction sequence POP DPH POP DPL will leave the stack pointer equal to the value 30H and the data pointer set to 0123H At this point the instruction POP SP will leave the stack pointer set to 20H Note that in this special case the stack pointer was decremented to 2FH ...

Page 191: ...dressed by the stack pointer Otherwise no flags are affected Example On entering an interrupt routine the stack pointer contains 09H The data pointer holds the value 0123H The instruction sequence PUSH DPL PUSH DPH will leave the stack pointer set to 0BH and store 23H and 01H in internal RAM locations 0AH and 0BH respectively Operation PUSH SP SP 1 SP direct Bytes 2 Cycles 2 Encoding 1 1 0 0 0 0 0...

Page 192: ... address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The stack pointer originally contains the value 0BH Internal RAM locations 0AH and 0BH contain the values 23H and 01H respectively The instruction RET will leave the stack pointer equal to the value 09H Program execution will continue at location 0123H Operation RET PC15 8 SP SP SP 1 PC7 0 SP S...

Page 193: ...ich is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt is pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed Example The stack pointer originally contains the value 0BH An interrupt was detected during the instruction ending at location 012...

Page 194: ...are rotated one bit to the left Bit 7 is rotated into the bit 0 position No flags are affected Example The accumulator holds the value 0C5H 11000101B The instruction RL A leaves the accumulator holding the value 8BH 10001011B with the carry unaffected Operation RL An 1 An n 0 6 A0 A7 Bytes 1 Cycles 1 Encoding 0 0 1 0 0 0 1 1 ...

Page 195: ... to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected Example The accumulator holds the value 0C5H 11000101B and the carry is zero The instruction RLC A leaves the accumulator holding the value 8AH 10001010B with the carry set Operation RLC An 1 An n 0 6 A0 C C A7 Bytes 1 Cycles 1 Encoding 0 0 1 1 0 0 1 1 ...

Page 196: ...re rotated one bit to the right Bit 0 is rotated into the bit 7 position No flags are affected Example The accumulator holds the value 0C5H 11000101B The instruction RR A leaves the accumulator holding the value 0E2H 11100010B with the carry unaffected Operation RR An An 1 n 0 6 A7 A0 Bytes 1 Cycles 1 Encoding 0 0 0 0 0 0 1 1 ...

Page 197: ...it to the right Bit 0 moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example The accumulator holds the value 0C5H 11000101B the carry is zero The instruction RRC A leaves the accumulator holding the value 62H 01100010B with the carry set Operation RRC An An 1 n 0 6 A7 C C A0 Bytes 1 Cycles 1 Encoding 0 0 0 1 0 0 1 1 ...

Page 198: ...r flags are affected Example The carry flag is cleared Output port 1 has been written with the value 34H 00110100B The instructions SETB C SETB P1 0 will leave the carry flag set to 1 and change the data output on port 1 to 35H 00110101B SETB C Operation SETB C 1 Bytes 1 Cycles 1 SETB bit Operation SETB bit 1 Bytes 2 Cycles 1 Encoding 1 1 0 1 0 0 1 1 Encoding 1 1 0 1 0 0 1 0 bit address ...

Page 199: ...tes following it Example The label RELADR is assigned to an instruction at program memory location 0123H The instruction SJMP RELADR will assemble into location 0100H After the instruction is executed the PC will contain the value 0123H Note Under the above conditions the instruction following SJMP will be at 102H Therefore the displacement byte of the instruction will be the relative offset 0123H...

Page 200: ...bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or immediate Example The accumulator holds 0C9H 11001001B register 2 holds 54H 01010100B and the car...

Page 201: ...Operation SUBB A A C direct Bytes 2 Cycles 1 SUBB A Ri Operation SUBB A A C Ri Bytes 1 Cycles 1 SUBB A data Operation SUBB A A C data Bytes 2 Cycles 1 Encoding 1 0 0 1 0 1 0 1 direct address Encoding 1 0 0 1 0 1 1 i Encoding 1 0 0 1 0 1 0 0 immediate data ...

Page 202: ...our bit fields of the accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected Example The accumulator holds the value 0C5H 11000101B The instruction SWAP A leaves the accumulator holding the value 5CH 01011100B Operation SWAP A3 0 A7 4 A7 4 A3 0 Bytes 1 Cycles 1 Encoding 1 1 0 0 0 1 0 0 ...

Page 203: ...n operand can use register direct or register indirect addressing Example R0 contains the address 20H The accumulator holds the value 3FH 00111111B Internal RAM location 20H holds the value 75H 01110101B The instruction XCH A R0 will leave RAM location 20H holding the value 3FH 00111111 B and 75H 01110101B in the accumulator XCH A Rn Operation XCH A Rn Bytes 1 Cycles 1 XCH A direct Operation XCH A...

Page 204: ...Semiconductor Group 204 Instruction Set XCH A Ri Operation XCH A Ri Bytes 1 Cycles 1 Encoding 1 1 0 0 0 1 1 i ...

Page 205: ...ddressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affected Example R0 contains the address 20H The accumulator holds the value 36H 00110110B Internal RAM location 20H holds the value 75H 01110101B The instruction XCHD A R0 will leave RAM location 20H holding the value 76H 01110110B and 35H 00110101B in the accumulator Operation XCHD A...

Page 206: ...to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3H 11000011B and register 0 holds 0AAH 10101010B then the instruction XRL A R0 will leave the accumulator holding the value 69H 01101001B When the destination is a directly addressed byte this instruction can complement combinations of bits...

Page 207: ...i Operation XRL A A Ri Bytes 1 Cycles 1 XRL A data Operation XRL A A data Bytes 2 Cycles 1 XRL direct A Operation XRL direct direct A Bytes 2 Cycles 1 Encoding 0 1 1 0 0 1 0 1 direct address Encoding 0 1 1 0 0 1 1 i Encoding 0 1 1 0 0 1 0 0 immediate data Encoding 0 1 1 0 0 0 1 0 direct address v v v v ...

Page 208: ...Semiconductor Group 208 Instruction Set XRL direct data Operation XRL direct direct data Bytes 3 Cycles 2 Encoding 0 1 1 0 0 0 1 1 direct address immediate data v ...

Page 209: ...DDC A data Add immediate data to A with carry flag 2 1 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 1 SUBB A Ri Subtract indirect RAM from A with borrow 1 1 SUBB A data Subtract immediate data from A with borrow 2 1 INC A Increment accumulator 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 1 INC Ri Increment indire...

Page 210: ... OR immediate data to accumulator 2 1 ORL direct A OR accumulator to direct byte 2 1 ORL direct data OR immediate data to direct byte 3 2 XRL A Rn Exclusive OR register to accumulator 1 1 XRL A direct Exclusive OR direct byte to accumulator 2 1 XRL A Ri Exclusive OR indirect RAM to accumulator 1 1 XRL A data Exclusive OR immediate data to accumulator 2 1 XRL direct A Exclusive OR accumulator to di...

Page 211: ... direct data Move immediate data to direct byte 3 2 MOV Ri A Move accumulator to indirect RAM 1 1 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate data to indirect RAM 2 1 MOV DPTR data16 Load data pointer with a 16 bit constant 3 2 MOVC A A DPTR Move code byte relative to DPTR to accumulator 1 2 MOVC A A PC Move code byte relative to PC to accumulator 1 2 MOVX A Ri Mo...

Page 212: ...Move direct bit to carry flag 2 1 MOV bit C Move carry flag to direct bit 2 2 ACALL addr11 Absolute subroutine call 2 2 LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LJMP addr16 Long iump 3 2 SJMP rel Short jump relative addr 2 2 JMP A DPTR Jump indirect relative to the DPTR 1 2 JZ rel Jump if accumulator is zero 2...

Page 213: ...cle CJNE A data rel Compare immediate to A and jump if not equal 3 2 CJNE Rn data rel Compare immed to reg and jump if not equal 3 2 CJNE Ri data rel Compare immed to ind and jump if not equal 3 2 DJNZ Rn rel Decrement register and jump if not zero 2 2 DJNZ direct rel Decrement direct byte and jump if not zero 3 2 NOP No operation 1 1 ...

Page 214: ... 80C535 is a powerful member of the Siemens SAB 8051 family of 8 bit microcontrollers It is designed in Siemens ACMOS technology and is functionally compatible with the SAB 80515 80535 devices designed in MYMOS technology The SAB 80C515 80C535 is a stand alone high performance single chip microcontroller based on the SAB 8051 80C51 architecture While maintaining all the SAB 80C51 operating charact...

Page 215: ...Device Specifications Semiconductor Group 215 ...

Page 216: ...to 85 C SAB 80C535 N T40 85 Q 67120 C0510 P LCC 68 for external memory 12 MHz ext temperature 40 to 85 C SAB 80C515 16 N Q 67120 DXXXX P LCC 68 with mask programmable ROM 16 MHz SAB 80C535 16 N Q 67120 C0509 P LCC 68 for external memory 16 MHz SAB 80C535 16 N T40 85 Q 67120 C0562 P LCC 68 for external memory 16 MHz ext temperature 40 to 85 C SAB 80C535 20 N Q 67120 C0778 P LCC 68 for external memo...

Page 217: ...Device Specifications Semiconductor Group 217 Pin Configuration P LCC 68 ...

Page 218: ... PSEN P2 7 A15 N C N C P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 VAREF N C VAGND P6 7 AIN7 P6 5 AIN5 P6 6 AIN6 P6 4 AIN4 P6 3 AIN3 RESET P6 2 AIN2 P6 0 AIN0 N C N C P3 1 TXD0 P6 1 AIN1 P3 0 RXD0 P3 2 INT0 P3 3 INT1 P3 4 T0 P3 5 T1 N C P3 7 RD P1 7 T2 P1 6 CLKOUT P1 4 INT2 P1 5 T2EX P1 3 INT6 CC3 P1 2 INT5 CC2 P3 6 WR P1 1 INT4 CC1 N C VCC VSS XTAL2 P1 0 INT3 CC0 N C XTAL1 P2 0 A8 P2 1 A9 P2 2 A10 P4 5 P...

Page 219: ...Device Specifications Semiconductor Group 219 Logic Symbol ...

Page 220: ...evel on this pin enables the use of the power saving modes idle mode and power down mode When PE is held on high level it is impossible to enter the power saving modes RESET 10 1 I Reset pin A low level on this pin for the duration of two machine cycles while the oscillator is running resets the SAB 80C515 A small internal pullup resistor permits power on reset using only a capacitor connected to ...

Page 221: ... port and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows R D P3 0 serial port s receiver data input asynchronous or data input output synchronous T D P3 1 serial port s transmitter data output asynchron...

Page 222: ...mpare pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows INT3 CC0 P1 0 interrupt 3 input compare 0 output capture 0 input INT4 CC1 P1 1 interrupt 4 input compare 1 output capture 1 input IN...

Page 223: ...45 I O Port 2 is an 8 bit bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current I I L in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte durin...

Page 224: ...cutes instructions from the internal ROM as long as the PC is less than 8192 When held low the SAB 80C515 fetches all instructions from external program memory For the SAB 80C535 this pin must be tied low P0 0 P0 7 52 59 52 59 I O Port 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is als...

Page 225: ...low will source current IIL in the DC characteristics because of the internal pullup resistors VCC 37 33 Supply voltage during normal idle and power down operation Internally connected to pin 68 VSS 38 34 Ground 0 V VCC 68 69 Supply voltage during normal idle and power down operation Internally connected to pin 37 N C 2 13 14 23 32 35 46 50 51 68 70 71 Not connected These pins of the P MQFP 80 pac...

Page 226: ...Device Specifications Semiconductor Group 226 Figure 1 Block Diagram ...

Page 227: ...tures of the SAB 80C515 are fully compatible with the SAB 80C51 features Instruction set External memory expansion interface port 0 and port 2 Full duplex serial port Timer counter 0 and 1 Alternate functions on port 3 The lower 128 bytes of internal RAM and the lower 4 Kbytes of internal ROM The SAB 80C515 additionally contains 128 bytes of internal RAM and 4 Kbytes of internal ROM which results ...

Page 228: ...the SAB 80C535 has no internal ROM pin EA must be tied low when using this component Data Memory The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SRF area While the upper 128 bytes o...

Page 229: ...Device Specifications Semiconductor Group 229 Figure 2 Memory Address Spaces ...

Page 230: ... Reset 80H 81H 82H 83H 84H 85H 86H 87H P0 1 SP DPL DPH reserved reserved reserved PCON 0FFH 07H 00H 00H XXH 2 XXH 2 XXH 2 000X 0000B 2 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH SCON 1 SBUF reserved reserved reserved reserved reserved reserved 00H XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH TCON 1 TMOD TL0 TL1 TH0 TH1 reserved reserved 00H 00H 00H 00H 00H 00H XXH 2 XXH 2 A0H A1H...

Page 231: ... 2 XXH 2 XXH 2 D8H D9H DAH DBH DCH DDH DEH DFH ADCON1 ADDAT DAPR P6 reserved reserved reserved reserved 00X0 0000B 2 00H 00H XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 C0H C1H C2H C3H C4H C5H C6H C7H IRCON 1 CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 00H 00H 00H 00H 00H 00H 00H 00H E0H E1H E2H E3H E4H E5H E6H E7H ACC 1 reserved reserved reserved reserved reserved reserved reserved 00H XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 XXH...

Page 232: ... XXH 2 F8H F9H FAH FBH FCH FDH FEH FFH P5 1 reserved reserved reserved reserved reserved reserved reserved 0FFH XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 XXH 2 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved Table 1 Special Function Register cont d Address Register Contents after Reset Address Register Contents after Reset ...

Page 233: ...ontrol Register Timer Control Register Timer 2 Control Register 0A8H 1 0B8H 1 0A9H 0B9H 0C0H 1 88H 1 0C8H 1 00H 00H 00H X000 0000B 2 XX00 0000B 3 00H 00H 00H Compare Capture Unit CCU CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON Comp Capture Enable Reg Comp Capture Reg 1 High Byte Comp Capture Reg 2 High Byte Comp Capture Reg 3 High Byte Comp Capture Reg 1 Low Byte Comp Capture Reg 2 ...

Page 234: ...l Control Reg 0D8H 1 87H 99H 98H 1 00X0 0000B 2 000X 0000B 2 0XXH 3 00H Timer 0 Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer Control Register Timer 0 High Byte Timer 1 High Byte Timer 0 Low Byte Timer 1 Low Byte Timer Mode Register 88H 1 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Watchdog IEN0 2 IEN1 2 IP0 2 IP1 2 Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 In...

Page 235: ...s not necessary to select these modes by software the voltages applied at port 6 pins can be converted to digital values using the A D converter and at the same time the pins can be read via SFR P6 It must be noted however that the results in port P6 bits will be indeterminate if the levels at the corresponding pins are not within their respective VIL VIH specifications Furthermore it is not possi...

Page 236: ...ctable gate function and compare capture and reload functions Corresponding to the 16 bit timer register there are four 16 bit capture compare registers one of them can be used to perform a 16 bit reload on a timer overflow or external event Each of these registers corresponds to a pin of port 1 for capture input compare output Figure 3 shows a block diagram of timer counter 2 Reload A 16 bit relo...

Page 237: ... 2 registers matches one of the stored values an appropriate output signal is generated and an interrupt is requested Two compare modes are provided Mode 0 Upon a match the output signal changes from low to high It goes back to a low level when timer 2 overflows Mode 1 The transition of the output signal can be determined by software A timer 2 overflow causes no output change Figure 3 Block Diagra...

Page 238: ...80C515 has eight multiplexed analog inputs Port 6 and uses the successive approximation method There are three characteristic time frames in a conversion cycle see A D converter characteristics the conversion time tC which is the time required for one conversion the sample time tS which is included in the conversion time and is measured from the start of the conversion the load time tL which in tu...

Page 239: ...Device Specifications Semiconductor Group 239 Figure 4 Block Diagram of the A D Converter ...

Page 240: ...e combined with the corresponding alternate functions compare output and capture input on port 1 For programming of the priority levels the interrupt vectors are combined to pairs Each pair can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1 Figure 6 shows the priority level structure Table 3 Interrupt Sou...

Page 241: ...Device Specifications Semiconductor Group 241 Figure 5 Interrupt Request Sources ...

Page 242: ...Device Specifications Semiconductor Group 242 Figure 6 Interrupt Priority Level Structure ...

Page 243: ...S technology of the SAB 80C515 allows two new power saving modes of the device The idle mode and the power down mode These modes replace the power down supply mode via pin VPD of the SAB 80515 NMOS The SAB 80C515 is supplied via pins VCC also during idle and power down operation However there are applications where unintentional entering of these power saving modes must be absolutely avoided Such ...

Page 244: ...ther provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running Table 4 SFR PCON 87H SMOD PDS IDLS GF1 GF0 PDE IDLE 87H 7 6 5 4 3 2 1 0 Symbol Pos...

Page 245: ... at logic high levels see table 5 As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event r...

Page 246: ...e RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Power Down Mode In the power down mode the on chip oscillator is stopped Therefore all functions are stopped only the contents of...

Page 247: ...es no VB B pin be cause the die s substrate is internally connected to VCC Furthermore the RAM backup power supply via pin VPD is replaced by the software controlled power down mode and power supply via VCC Therefore pins VB B and VPD of the NMOS version SAB 80515 are used for other functions in the SAB 80C515 Pin 4 the former pin VPD is the new PE pin which enables the use of the power saving mod...

Page 248: ...ro controller A pocket guide is available which contains the complete instruction set in functional and hexa decimal order Furtheron it provides helpful information about Special Function Registers In terrupt Vectors and Assembler Directives Literature Information Title Ordering No Microcontroller Family SAB 8051 Pocket Guide B158 H6579 X X 7600 ...

Page 249: ...e those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions VIN VCC or VIN VSS the Voltage on VCC pins with respect to ground VSS must not exeed the values defined by the absolute maximum ratings DC Characteristics VCC 5 V 10 VSS 0 V T A 0 to 70 C for th...

Page 250: ...5 IIL 10 70 µA VIN 0 45 V Input low current to RESET for reset IIL2 10 100 µA VIN 0 45 V Input low current XTAL2 II L3 15 µA VIN 0 45 V Input low current PE II L4 20 µA VIN 0 45 V Logical 1 to 0 transition current ports 1 2 3 4 5 ITL 65 650 µA VIN 2 V Input leakage current port 0 port 6 AN0 7 EA IL I 1 µA 0 45 VI N VCC Pin capacitance CI O 10 pF fC 1 MHz TA 25 C Power supply current Active mode 12...

Page 251: ...9 VCC specification when the address bits are stabilizing 3 Power down ICC is measured with EA Port 0 Port 6 VCC XTAL1 N C XTAL2 VSS RESET VCC VAGND VSS all other pins are disconnected 4 ICC active mode is measured with XTAL2 driven with the clock signal according to the figure below XTAL1 N C EA Port 0 Port 6 VCC RESET VSS all other pins are disconnected ICC might be slightly higher if a crystal ...

Page 252: ...EF VCC VI ntAGND VAGND VSS7 VAREF supply current IREF 5 mA 8 Internal reference error VI nt REFERR 30 mV 8 7 The output impedance of the analog source must be low enough to assure full loading of the sample capacitance CI during load time tL After charging of the internal capacitance CI in the load time tL the analog input must be held constant for the rest of the sample time tS 8 The differential...

Page 253: ...L 30 ns Address hold after ALE tLLAX 48 tC LCL 35 ns ALE to valid instruction in tLLIV 233 4 tCLCL 100 ns ALE to PSEN tLLPL 58 tC LCL 25 ns PSEN pulse width tPLPH 215 3 tC LCL 35 ns PSEN to valid instruction in tPLIV 150 3 tC LCL 100 ns Input instruction hold after PSEN tPXIX 0 0 ns Input instruction float after PSEN tPXIZ 1 63 tC LCL 20 ns Address valid after PSEN tPXAV 1 75 tC LCL 8 ns Address t...

Page 254: ...D to valid data in tRLDV 252 5 tCLCL 165 ns DATA hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 97 2 tCLCL 70 ns ALE to valid data in tLLDV 517 8 tCLCL 150 ns Address to valid data in tAVDV 585 9 tCLCL 165 ns ALE to WR or RD tLLWL 200 300 3 tCLCL 50 3 tCLCL 50 ns WR or RD high to ALE high tWHLH 43 123 tCLCL 40 tCLCL 40 ns Address valid to WR tAVWL 203 4 tCLCL 130 ns Data valid to WR transiti...

Page 255: ...alues Unit Variable clock Frequ 3 5 MHz to 12 MHz min max External Clock Drive Oscillator period tCLCL 83 3 285 ns Oscillator frequency 1 tCLCL 0 5 12 MHz High time tCHCX 20 ns Low time tCLCX 20 ns Rise time tCLCH 20 ns Fall time tCHCL 20 ns MCT00033 tCHCX tCLCX CHCL t CLCH t VCC tCLCL 0 5V 0 45V CC 0 7 V V 0 1 CC 0 2 ...

Page 256: ...meter Symbol Limit values Unit 12 MHz clock Variable clock 1 tCLCL 3 5 MHz to 12 MHz min max min max System Clock Timing ALE to CLKOUT tLLSH 543 7 tCLCL 40 ns CLKOUT high time tSHSL 127 2 tCLCL 40 ns CLKOUT low time tSLSH 793 10 tCLCL 40 ns CLKOUT low to ALE high tSLLH 43 123 tCLCL 40 tCLCL 40 ns ...

Page 257: ...o ALE t AVLL 33 tCLCL 30 ns Address hold after ALE t LLAX 28 tCLCL 35 ns ALE to valid instruction in t LLIV 150 4 tCLCL 100 ns ALE to PSEN t LLPL 38 tCLCL 25 ns PSEN pulse width t PLPH 153 3 tCLCL 35 ns PSEN to valid instruction in t PLIV 88 3 tCLCL 100 ns Input instruction hold after PSEN t PXIX 0 0 ns Input instruction float after PSEN t PXIZ 1 43 tCLCL 20 ns Address valid after PSEN t PXAV1 55 ...

Page 258: ... to valid data in tRLDV 148 5 tCLCL 165 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 55 2 tCLCL 70 ns ALE to valid data in tLLDV 350 8tCLCL 150 ns Address to valid data in tAVDV 398 9 tCLCL 165 ns ALE to WR or RD tLLWL 138 238 3 tCLCL 50 3 tCLCL 50 ns WR or RD high to ALE high tWHLH 23 103 tCLCL 40 tCLCL 40 ns Address valid to WR tAVWL 120 4 tCLCL 130 ns Data valid to WR transi tio...

Page 259: ...alues Unit Variable clock Frequ 3 5 MHz to 16 MHz min max External Clock Drive Oscillator period tCLCL 62 5 285 ns Oscillator frequency 1 tCLCL 0 5 16 MHz High time tCHCX 15 ns Low time tCLCX 15 ns Rise time tCLCH 15 ns Fall time tCHCL 15 ns MCT00033 tCHCX tCLCX CHCL t CLCH t VCC tCLCL 0 5V 0 45V CC 0 7 V V 0 1 CC 0 2 ...

Page 260: ...eter Symbol Limit values Unit 16 MHz clock Variable clock 1 tCLCL 3 5 MHz to 16 MHz min max min max System Clock Timing ALE to CLK OUT tLLSH 398 7 tCLCL 40 ns CLK OUT high time tSHSL 85 2 tCLCL 40 ns CLK OUT low time tSLSH 585 10 tCLCL 40 ns CLK OUT low to ALE high tSLLH 23 103 tCLCL 40 tCLCL 40 ns ...

Page 261: ...clock Variable clock 1 tCLCL 3 5 MHz to 20 MHz min max min max Program Memory Characteristics ALE pulse width tLHLL 60 2 tCLCL 40 ns Address setup to ALE tAVLL 20 tCLCL 30 ns Address hold after ALE tLLAX 20 tCLCL 30 ns ALE low to valid instr in tLLIV 100 4 tCLCL 100 ns ALE to PSEN tLLPL 25 tCLCL 25 ns PSEN pulse width tPLPH 115 3 tCLCL 35 ns PSEN to valid instr in tPLIV 75 3 tCLCL 75 ns Input inst...

Page 262: ...to valid data in tRLDV 155 5 tCLCL 95 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 40 2 tCLCL 60 ns ALE to valid data in tLLDV 250 8 tCLCL 150 ns Address to valid data in tAVDV 285 9 tCLCL 165 ns ALE to WR or RD tLLWL 100 200 3 tCLCL 50 3 tCLCL 50 ns Address valid to WR or RD tAVWL 70 4 tCLCL 130 ns WR or RD high to ALE high tWHLH 20 80 tCLCL 30 tCLCL 30 ns Data valid to WR transit...

Page 263: ...d External Clock Cycle Parameter Symbol Limit Values Unit Variable clock 1 tCLCL 3 5 MHz to 20 MHz min max External Clock Drive Oscillator period tCLCL 50 285 ns High time tCHCX 12 tCLCL tCLCX ns Low time tCLCX 12 tCLCL tCHCX ns Rise time tCLCH 12 ns Fall time tCHCL 12 ns ...

Page 264: ...rameter Symbol Limit values Unit 20 MHz clock Variable clock 1 tCLCL 3 5 MHz to 20 MHz min max min max System Clock Timing ALE to CLKOUT tLLSH 310 7 tCLCL 40 ns CLKOUT high time tSHSL 60 2 tCLCL 40 ns CLKOUT low time tSLSH 460 10 tCLCL 40 ns CLKOUT low to ALE high tSLLH 10 90 tCLCL 40 tCLCL 40 ns ...

Page 265: ...ess to valid data tAVQV 48 tCLCL ns ENABLE to valid data tELQV 48 tCLCL ns Data float after ENABLE tEHOZ 0 48 tCLCL ns Oscillator frequency 1 tCLCL1 4 6 MHz Address to valid data tAVQV 48 tCLCL ns MCT00049 t AVQV tEHQZ t ELQV Address Data OUT P1 0 P1 7 P2 0 P2 4 Port 0 P2 7 ENABLE Inputs P2 5 P2 6 PSEN ALE EA RESET P0 0 P0 7 D0 D7 Data P2 0 P2 4 A8 A12 Address P1 0 P1 7 A0 A7 V IH SS V VSS ...

Page 266: ...L t A8 A15 A8 A15 A0 A7 Instr IN A0 A7 Port 0 t AVLL PLPH t t LLPL t LLIV t PLIV t AZPL t LLAX t PXIZ t PXIX t AVIV t PXAV MCT00097 ALE PSEN Port 2 WHLH t Port 0 RD t LLDV tRLRH t LLWL tRLDV t AVLL t LLAX2 t RLAZ tAVWL t AVDV tRHDX tRHDZ A0 A7 from Ri or DPL from PCL A0 A7 Instr IN Data IN A8 A15 from PCH P2 0 P2 7 or A8 A15 from DPH ...

Page 267: ...0 A7 Instr IN Data OUT A8 A15 from PCH P2 0 P2 7 or A8 A15 from DPH AC inputs during testing are driven at VCC 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at VIH min for a logic 1 and VIL max for a logic 0 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV deviation from the load voltage...

Page 268: ...Device Specifications Semiconductor Group 268 AC Testing Input Output Waveforms AC Testing Float Waveforms ...

Page 269: ...or Group 269 Package Outlines Plastic Package P LCC 68 SMD Plastic Leaded Chip Carrier Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information Dimensions in mm SMD Surface Mounted Device ...

Page 270: ...Group 270 Package Outlines Plastic Package P MQFP 80 SMD Plastic Metric Quad Flat Package Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information Dimensions in mm SMD Surface Mounted Device ...

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