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S3C2501X
ETHERNET CONTROLLER
7-27
7.4.2.4 MAC Transmit Control Register
Table 7-18. MACTXCON Register
Registers
Address
R/W
Description
Reset Value
MACTXCONA
0xF00B0008
R/W
Transmit control
0x00000000
MACTXCONB
0xF00D0008
R/W
Transmit control
0x00000000
Bit Number
Bit Name
Description
[0]
Transmit enable (MTxEn)
Set this bit to enable transmission. To stop transmission
immediately, clear the transmit enable bit to '0'.
[1]
Transmit halt request
(MTxHalt)
Set this bit to halt the transmission after completing the
transmission of any current frame.
[2]
Suppress padding (MNoPad)
Set this bit not to generate pad bytes for frames of less than
64 bytes.
[3]
Suppress CRC (MNoCRC)
Set this bit to suppress addition of a CRC at the end of a
frame.
[4]
Fast back-off (MFBack)
Set this bit to use faster back-off times for testing.
[5]
No defer (MNoDef)
Set this bit to disable the defer counter. (The defer counter
keeps counting until the carrier sense (CrS) bit is turned off.)
[6]
Send Pause (MSdPause)
Set this bit to send a pause command or other MAC control
frame. The send pause bit is automatically cleared when a
complete MAC control frame has been transmitted. Writing a
'0' to this register bit has no effect.
[7]
MII 10M-b/s SQE test mode
enable (MSQEn)
Set this bit to enable MII 10M-b/s SQE test mode.
[31:8]
Reserved
Not applicable.
Summary of Contents for S3C2501X
Page 18: ......
Page 275: ...MEMORY CONTROLLER S3C2501X 5 60 NOTES ...
Page 289: ...I2C CONTROLLER S3C2501X 6 14 NOTES ...
Page 373: ...GDMA CONTROLLER S3C2501X 9 24 NOTES ...
Page 435: ...I O PORTS S3C2501X 12 12 NOTES ...