Samsung S3C2501X, User Manual

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SYSTEM CONFIGURATION S3C2501X
4-14
NOTES:
1. CPU PLL block can generate eight clock frequencies between 166MHz and 33MHz according to the
CPU_FREQ[2:0] pins out of the 10MHz XCLK input clock frequency.
2. If CLKSEL, CPU PLL, or BUS PLL go into the state of power down.
3. Three pins of CPU_FREQ[2:0] can control the multiplication factor of the CPU PLL block.
4. The PHY_FREQ pin controls the frequency of the PHY PLL.
5. The system configuration register CLKCON[15:0] can divide the ARM9 clock and the system clock. If all bits are 0,
non-divided clock is used.Only one bit can be set in CLKCON[15:0]. That is, the clock dividing value is defined as
1, 2, 4, 8, 16, .... The internal clock is (PLL output clock between 166MHz and 33MHz) / (1).
6. The CLKCON[15:0] register, CLKMOD[1:0] pins and CPU_FREQ[2:0] pins can control the AMBA clock divider.
The CLKMOD[1:0] pins and BUS_FREQ[2:0] pins can generate the various AMBA bus clock frequecies referring
to the Table 3. The CLKCON[15:0] register can divide the various AMBA clock frequecies of the Table 4-3.
7. All PLL can be controlled by either pin setting or register setting.
{CLKCON[15:0], CLKMOD[1:0],
BUS_FREQ[2:0]}
CPU PLL
166-33
MHz
0
1
ARM940T
Block
ARM
Clock
Divider
CPU_FREQ[2:0] or
pdown
CLKSEL
CLKCON[15:0]
BUS PLL
Block
AMBA
Divider
BUS_FREQ[2:0] or
pdown
CLKSEL
0
1
1
PLL_TEST
Clock
Divider
pin
PLL_TEST & PP[1:0]
PHY PLL
20/25
0
1
PPLLCON
pdown
XCLK
PHY_CLKO
MHz
Figure 4-5. Shows the Clock Generation Logic of the S3C2501X