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RZ/G1E

5. Pin Function Controller (PFC)

R01UH0544EJ0100 Rev.1.00

5-66

Sep 30,2016

5.3.37

IICDVFS and TDBG IO cell control register (IOCTRL7)

Function: IOCTRL7 controls the driving abilities of pins in use for the IIC and IICDVFS interfaces. This register is

internal use and reserved; the value of this register should not be changed.

Bit:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

gpreg_mse

l03_p

a_iic

dvfs

b_iic

dvfs

Initial value: 0

R/W: R/

R/
W

Bit Bit

Name

Initial
Value

R/W Description

31 to 13 —

All 0

R/W

—

12 gpreg_msel03_p

[15]

R/W

Debug monitor function:
0: Use DU pins for debug monitor function.
1: Use SDHI pins for debug monitor function.

11 to 8

—

All 0

R/W

—

conta_iicdvfs

R/W

Control TOF value of IICDVFS IO cell (TOF: Output fall time from
VIH min to VIL max OR from 0.7VPU to 0.3VPU )
0: 0.3VPU
1: 0.7VPU

6 contb_iicdvfs

R/W

Control VIH/VIL value of IICDVFS IO cell (VIH: High level input
voltage ; VIL: Low level input voltage )
0: VIL
1: VIH

5 to 0

—

All 0

R/W

—

Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately

before setting this register.

Summary of Contents for RZ/G1E

Page 1: ...he product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp RZ G1E User s Manual Hardware Rev 1 00 Sep 2016 for Rich Graphics Applications RZ G Series Specifications of Individual RZ G Series Product ...

Page 2: ...e range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as t...

Page 3: ... supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provid...

Page 4: ...sions of these documents Document Type Description Document Title Document No User s manual for specifications of individual RZ G Series product Overview of hardware pin assignments pin multiplexing and pin function controller RZ G1E User s Manual Hardware R01UH0544EJ0 100 Rev 1 00 This user s manual User s manual for specifications common to RZ G Series products Hardware specifications address ma...

Page 5: ...register description includes a bit chart illustrating the arrangement of bits and a table of bits describing the meanings of the bit settings All trademarks and registered trademarks are the property of their respective owners ...

Page 6: ...n Controller PFC 5 1 5 1 Overview 5 1 5 1 1 Features 5 1 5 2 Register Configuration 5 2 5 3 Register Description 5 4 5 3 1 LSI Multiplexed Pin Setting Mask Register PMMR 5 5 5 3 2 GPIO Peripheral Function Select Register 0 GPSR0 5 5 5 3 3 GPIO Peripheral Function Select Register 1 GPSR1 5 7 5 3 4 GPIO Peripheral Function Select Register 2 GPSR2 5 9 5 3 5 GPIO Peripheral Function Select Register 3 ...

Page 7: ... 3 MOD_SEL3 5 44 5 3 26 LSI Pin Pull Up Control Register 0 PUPR0 5 46 5 3 27 LSI Pin Pull Up Control Register 1 PUPR1 5 48 5 3 28 LSI Pin Pull Up Control Register 2 PUPR2 5 50 5 3 29 LSI Pin Pull Up Control Register 3 PUPR3 5 52 5 3 30 LSI Pin Pull Up Control Register 4 PUPR4 5 54 5 3 31 LSI Pin Pull Up Control Register 5 PUPR5 5 56 5 3 32 LSI Pin Pull Up Control Register 6 PUPR6 5 58 5 3 33 SD Co...

Page 8: ...ay Output 2 channels Video Input Sound processing unit SD card host interface USB2 0 interfaces and CAN interface Also a full implementation of the extremely expandable and Internal AXI bus has been adopted for the RZ G1E This bus structure is optimized for maximum system performance leading to the realization of high performance and cost effective premium in vehicle infotainment systems Notes 1 A...

Page 9: ...GPIO ADG L2C DDR3 SDRAM SuperH RISC Engine SH 4A 32 bit CAN 2 ch 6 ch IE BUS WDT JTAG Secure WDT TPU Secure timer Secure up time clock 4 ch CMT0 2 ch CMT1 8 ch 2 ch 30 ch MLP USB2 0 Host Func PHY USB2 0 Host VSP1 VCP3 Ethernet AVB Ethernet MAC FDP1 2D DMAC 1 ch IPMMU INTC VIN 2 ch IMR LX2 1 ch Audio DSP DCU 3DGE SDHI DU Audio DMAC 13 ch Audio DMAC peripheral peripheral 29 ch I2C 6 ch SCIF 6 ch SCI...

Page 10: ...tion System CPU Cortex A7 ARM Cortex A7 Dual MPCore 1 0 GHz L1 I D cache 32 32 KBytes L2 cache 512 KBytes NEON VFPv4 supported Security extension supported ARM debugger CoreSight CoreSight system compliant JTAG SWD I F supported CoreSight ETR 16 KBytes for program flow trace CoreSight ETR 4 KBytes for system trace ...

Page 11: ... external modules Includes Boot Address Register etc Pin function controller PFC Setting multiplexed pin functions for LSI pins Function of the RZ G1E pin selectable by setting the registers in the PFC module Module selection Enable and disable the functions of RZ G1E LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module Pull up control fo...

Page 12: ...t in cycle unit and the maximum value is 15 EX_WAIT pin can be used for wait state insertion Connectable bus widths 16 bits or 8 bits Burst ROM interface Wait states can be inserted through register settings Number of bursts can be set through register settings Connectable bus widths 16 bits or 8 bits Byte control SRAM interface available with areas 1 and 6 only Byte control SRAM interface Wait st...

Page 13: ...er of transfers 16 M 16 777 216 transfers 64M 67 108 864 transfers 64 M transfers supported only for LBSC DMAC00 Minimum number of transfers One Address mode Dual address mode Transfer modes Single transfer mode continuous transfer mode Transfer end interrupt Occurs at the end of the number of transfers specified in the register DDR3 SDRAM bus state controller DBSC 1 channel 32 bit bus DDR3 SDRAM ...

Page 14: ...uest to CPU at the end of data transfer Repeat function Automatically resets the transfer source destination and count at the end of DMA transfer by descriptor function Descriptor function each channel supported MMU each channel supported Channel bandwidth arbiter each channel Direct memory access controller Audio DMAC 13 channels for Audio domain Address space 4 GBytes on architecture Data transf...

Page 15: ...upt request to CPU at the end of data transfer IPMMU An IPMMU is a memory management unit MMU which provides address translation and access protection functionalities to processing units and interconnect networks Interrupt controller INTC INTC SYS 10 interrupt pins which can detect external interrupts Fall rise high level low level detection is selectable On chip peripheral interrupts Priority can...

Page 16: ...anes which can display 256 of 260 thousands colors at the same time Digital RGB Two output channel Output on rising and falling edges of the synchronizing signal resolution for the same display 8 bit precision for each RGB color Blending ratio settings Number of color palette planes with blending ratio 4 Dot clock Switchable between external input and internal clock Color management γ correction g...

Page 17: ... 12 bits Y 12 bits CbCr format 18 bit RGB666 24 bit RGB888 Clipping function Up to 2048 2048 Horizontal scaling Uses a 9 tap multi phase filter Up to two times but only scaling down is possible for HD1080i or HD720P data Vertical scaling Scaling by linear interpolation Up to three times but only scaling down is possible for HD1080i or HD720P data Output format RGB 565 ARGB 1555 YCbCr422 RGB888 cha...

Page 18: ...ersion and changes to the number of colors by dithering Color keying 2 Full HD Video Processing Up and down scaling with arbitrary scaling ratio Super resolution processing Blending of four picture layers and raster operations ROPs 3 Full HD Picture Quality Color Correction with 1D 3D Look Up Table LUT Dynamic γ correction and gain correction Correction of color to adjust skin tones or colors in m...

Page 19: ...icture by picture basis Encodes decodes data one picture frame or field at a time High picture quality Supports the H 264 high efficiency coding tools CABAC 8 8 frequency conversion and quantization matrix High efficiency motion vector detection by a combination of discrete search and trace search Highly efficient real time intra prediction by Prediction from Original Image POI Optimal mode select...

Page 20: ...extraction function Capable of extracting an image and storing it as a separate image in the RAM Image rotation reversal function Reverses an image vertically horizontally or rotates it by 90 270 Simple scaling function Capable of scaling an image two times in the X or Y direction Format conversion Supports conversion from RGB to RGB and from YCbCr to YCbCr ...

Page 21: ...ter is written in the equivalent up sampling cases Automatically generates antialiasing filter coefficients For monaural to eight channel sound sources Channel count conversion unit CTU Downmixing and splitter functions Conversion of eight input channels into four output channels Conversion of six input channels into two output channels Conversion of two input channels into four sets of two output...

Page 22: ... Serial sound interface SSI Operating mode non compressed mode Not support compressed mode Supports versatile serial audio formats I2S left justified right justified Supports master slave functions Programmable word clock bit clock generation functions Multichannel format functions up to four channels Supports 8 16 18 20 22 24 32 bit data formats Supports TDM mode Supports WS continue mode The DMA...

Page 23: ... Support SDR104 class transfer rate at Max 97 5 MBytes sec 195 MHz and SDXC Does not support CPRM Interfaces 1 and 2 Support SDR50 class transfer rate at Max 48 MBytes sec 97 5 MHz and SDXC Does not support CPRM Supports SD memory SDIO interface 1 4 bit SD buses Error check function CRC7 command response CRC16 data Card detection function Supports write protection Multi media card interface MMCIF ...

Page 24: ... ID or both IDs Selectable ID priority mode or mailbox number priority mode Sleep mode for reducing power consumption Ethernet AVB Supports IEEE802 1BA IEEE802 1AS IEEE802 1Qav and IEEE1722 functions Supports transfer at 1000 Mbps and 100 Mbps Magic packet detection Supports Reception Filtering to separate streaming frames from different sources Supports interface conforming to IEEE802 3 PHY GMII ...

Page 25: ...lock Compare match function provided Interrupt requests Compare match timer 1 CMT1 Eight channels 48 bit timer 16 bits 32 bits 48 bits can be selected Source clock RCLK system clock Compare match function provided Interrupt requests Timer unit TMU 4 sets of 3 channel 32 bit timer Auto reload type 32 bit down counter Internal prescaler Interrupt request 2 channels for input capture ...

Page 26: ...tion from the system clock Serial communication interface with FIFO SCIFA 6 channels Internal 64 Byte transmit receive FIFOs High speed UART Internal prescaler Clock synchronous serial communications possible Support edge selection function Interrupt request DMAC request and DMA multi Byte transfer supported Asynchronous mode Clock synchronous mode Serial communication interface with FIFO SCIFB 3 ...

Page 27: ...onous communication There is a single serial data communication format for clock synchronous serial communication Data length 8 bits Receive error detection Overrun errors Full duplex communication capability The SCIF has an independent transmitter and receiver that enable simultaneous transmission and reception The transmitter and receiver both have a 16 stage FIFO buffer structure enabling conti...

Page 28: ...l duplex communication On chip baud rate generator enabling any bit rate to be selected Eight interrupt sources DMA data transfer Modem control functions HRTS and HCTS are stored The amount of data in the transmit receive FIFO registers and the number of receive errors in receive data in the receive FIFO register are available A receive data ready DR or a timeout error TO can be detected during re...

Page 29: ...TAG interface for CoreSight Process 28nm Si CMOS Package FC BGA2121 501 1 4 Power Supply Voltages and Temperature Range Power supply voltage typ 1 8 V ETM SD LVCMOS I F Xtal JTAG Trace and RST 1 03 V core 1 5 V DDR3 I O SSTL Mode DDR3 3 3 V Others Temperature range Ta 40 C to 85 C Tc 40 C to 105 C ...

Page 30: ...RZ G1E 2 Area Map R01UH0544EJ0100 Rev 1 00 2 1 Sep 30 2016 2 Area Map See section 2 Area Map in the RZ G Series User s Manual Hardware ...

Page 31: ...D VSS VSS VDD VSS R VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VSS VSS VDD VSS T HSCIF0_ HSCK HSCIF0_ HRTS HSCIF0_ HCTS HSCIF0_ HTX ETH_MDIO VSS VSS VSS VDD VSS U HSCIF0_HRX ETH_TXD0 ETH_TX_EN ETH_RXD1 ETH_RX_ER VCCQ18 V ETH_REF_ CLK ETH_TXD1 ETH_RXD0 ETH_CRS_ DV ETH_LINK VCCQ18 W VI0_VSYNC VI0_FIELD VI0_DATA5 VI0_B5 ETH_MAGIC ETH_MDC VSS Y VI0_HSYNC VI0_DATA6 VI0_B6 VI0_DATA4 VI0_B4 I2C0_SDA I2C0_SCL VSS VSS ...

Page 32: ...1_DP USB1_DM N VDD VSS VSS VD331 TMS TDO AVDD USB0_DP USB0_DM P VDD VSS VSS VD181 BSMODE TDI NMI VSS VSS R VDD VSS VSS VCCQ18 USB1_PWEN USB1_OVC EXREFIN VSS USB_XTAL USB_EXTAL T VCCQ18 USB0_PWEN USB0_OVC ACK VSS VSS U VCCQ VDD_MLB PLL IIC1_SDA I2C7 PRESET XTAL EXTAL V VSS_MLB PLL IIC1_SCL I2C7 MSIOF0_SS2 MSIOF0_ TXD MSIOF0_ RXD VSS W VSS VCCQ VCCQ VSS VSS VSS VSS SSI_SDATA4 MSIOF0_SS1 HSCIF1_ HCTS...

Page 33: ...ning Mode or Step Up Mode 0 Free running mode 1 Step up mode MD3 MD2 MD1 Boot Device Selection 0 0 0 area 0 boot boot from external MaskROM 0 1 0 QSPI 48 75 MHz 16 KB transfer 0 0 1 Reserved 0 1 1 Reserved 1 0 0 QSPI 39 MHz 16 KB transfer 1 0 1 QSPI 78 MHz 16 KB transfer 1 1 0 QSPI 39 MHz 4 KB transfer 1 1 1 Reserved MD4 Area Division 0 Area 0 64 Mbytes 1 Area 0 128 Mbytes MD5 Reserved fixed to 1 ...

Page 34: ...ode Normal mode 1 00 Coresight debug port Normal mode 1 00 Reserved Reserved Reserved 01 0 Coresight debug port Normal mode Normal mode 1 01 Reserved Normal mode 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved MD14 MD13 Resonator Input Clock Internal Divider PLL1 PLL0 PLL3 MD19 DDR3 1333 0 0 15 MHz 1 1 208 200 88 0 1 20 MHz 1 1 156 150 66 1 0 26 MHz 1 2 240 230 102 1 1 30 MHz 1 2 208 2...

Page 35: ...cified This indication is different from that of in section 5 Pin Function Controller PFC Rightmost column of table During POR Pin state during power on reset PRESET pin input is low level V power IOH Pin voltage power domain and output drive current nominal value respectively Pull up Internal pull up control function is available or not from a power on reset On Pull up control function is availab...

Page 36: ... X 28 DBSC3 L C11 M0CK1 1 5 1 35V VDDQ_M0 A8 M0A10 1 5 1 35V VDDQ_M0 O O L 9 DBSC3 X 29 DBSC3 L C10 M0CK1 1 5 1 35V VDDQ_M0 A9 M0A11 1 5 1 35V VDDQ_M0 O O L 10 DBSC3 H 30 DBSC3 L C15 M0CS0 1 5 1 35V VDDQ_M0 A6 M0A12 1 5 1 35V VDDQ_M0 O H O L 11 DBSC3 H 31 DBSC3 L E10 M0CS1 1 5 1 35V VDDQ_M0 B7 M0A13 1 5 1 35V VDDQ_M0 O H O L 12 DBSC3 L 32 DBSC3 L B16 M0ODT0 1 5 1 35V VDDQ_M0 D7 M0A14 1 5 1 35V VDD...

Page 37: ...50 DBSC3 P 70 DBSC3 Z F16 VDDQ_M0DPLL0 1 8V VDDQ_M0DPLL0 F24 M0DQ20 1 5 1 35V VDDQ_M0 P IO Z 51 DBSC3 P 71 DBSC3 Z F15 VSSQ_M0DPLL0 GND VDDQ_M0DPLL0 D24 M0DQ21 1 5 1 35V VDDQ_M0 P IO Z 52 DBSC3 P 72 DBSC3 Z C14 M0VREFDQ0 1 5 1 35V VDDQ_M0 B25 M0DQ22 1 5 1 35V VDDQ_M0 P IO Z 53 DBSC3 Z 73 DBSC3 Z B17 M0DQ8 1 5 1 35V VDDQ_M0 C24 M0DQ23 1 5 1 35V VDDQ_M0 IO Z IO Z 54 DBSC3 Z 74 DBSC3 Z D17 M0DQ9 1 5 ...

Page 38: ...M0DQ30 1 5 1 35V VDDQ_M0 IO Z 87 DBSC3 Z L25 M0DQ31 1 5 1 35V VDDQ_M0 IO Z 88 DBSC3 Z H25 M0DQS3 1 5 1 35V VDDQ_M0 IO Z 89 DBSC3 Z J25 M0DQS3 1 5 1 35V VDDQ_M0 IO Z 90 DBSC3 Z J22 M0DM3 1 5 1 35V VDDQ_M0 O Z 91 DBSC3 P J20 VDDQ_M0DPLL3 1 8V VDDQ_M0DPLL3 P 92 DBSC3 P H20 VSSQ_M0DPLL3 GND VDDQ_M0DPLL3 P 93 DBSC3 P C7 VDDQ_M0BKUP 1 5 1 35V VDDQ_M0BKUP P 3 3 DBSC3 Note No 88 and 89 M0DQS3 and M0DQS3 p...

Page 39: ... 109 Debug Z E9 VSS_CPGPLL0 GND VDD_CPGPLL0 P22 TDO 1 8V VCCQ18 4mA P O Z 98 PLL P 110 Debug I K15 L15 VDD_CPGPLL1 1 8V VDD_CPGPLL1 U23 ACK 1 8V VCCQ18 4mA P IO I On pull down 99 PLL P 111 USB I K16 L16 VSS_CPGPLL1 GND VDD_CPGPLL1 T25 USB_EXTAL 1 8V VCCQ18 P I 100 PLL P 112 USB O K12 L12 VDD_CPGPLL3 1 8V VDD_CPGPLL3 T24 USB_XTAL 1 8V VCCQ18 P O 101 PLL P 113 USB P K11 L11 VSS_CPGPLL3 GND VDD_CPGPL...

Page 40: ...I 124 USB 2 0 ch1 I M24 USB1_RREF 3 3V VCCQ I 125 USB 2 0 ch1 Z USB T21 USB1_PWEN GP5_26 3 3V VCCQ 4mA O L IO 126 USB 2 0 ch1 I USB T22 USB1_OVC GP5_27 3 3V VCCQ 4mA I I IO 127 INTC I S R23 NMI 1 8V VCCQ18 I S 128 SDHI0 I GPIO AE12 SD0_CLK GP6_0 1 8 3 3V VCCQ_SD0 16mA O IO I 129 SDHI0 I GPIO AD12 SD0_CMD GP6_1 1 8 3 3V VCCQ_SD0 16mA IO IO I Off 130 SDHI0 I GPIO AC11 SD0_DATA0 GP6_2 1 8 3 3V VCCQ_S...

Page 41: ...3 3V VCCQ_SD1 16mA I I O IO I Off 145 SDHI1Power P AC7 VCCQ_SD1 1 8 3 3V VCCQ_SD1 P 146 MMC SDHI2 I GPIO Z DBG AE10 MMC_CLK SD2_CLK GP6_16 1 8 3 3V VCCQ_MMC_SD2 16mA O O IO I 147 MMC SDHI2 I GPIO I DBG AD9 MMC_CMD SD2_CMD GP6_17 1 8 3 3V VCCQ_MMC_SD2 16mA IO IO IO I Off 148 MMC SDHI2 I GPIO I DBG AA9 MMC_D0 SD2_DATA0 GP6_18 1 8 3 3V VCCQ_MMC_SD2 16mA IO IO IO I Off 149 MMC SDHI2 I GPIO I DBG AA11 ...

Page 42: ...TC TMU PWM6 I GPIO B5 D7 IRQ3 TCLK1 PWM6_B GP0_7 3 3V VCCQ 8mA IO I I I O IO I On 165 LBSC HSCIF2 I2C1 I GPIO C4 D8 HSCIF2_HRX I2C1_SCL_B GP0_8 3 3V VCCQ 8mA IO I I IO IO I On 166 LBSC HSCIF2 I2C1 I GPIO A3 D9 HSCIF2_HTX I2C1_SDA_B GP0_9 3 3V VCCQ 8mA IO I O IO IO I On 167 LBSC HSCIF2 SCIF1 INTC PWM5 I GPIO E4 D10 HSCIF2_HSCK SCIF1_SCK_C IRQ6 PWM5_C GP0_10 3 3V VCCQ 8mA IO I IO IO I O IO I On 168 ...

Page 43: ...O L IO IO IO I On 184 LBSC MSIOF1 IIC0 I2C6 I GPIO H3 A11 MSIOF1_SYNC IIC0_SDA_B GP0_27 3 3V VCCQ 8mA O L IO IO IO I On 185 LBSC MSIOF1 SCIFA5 I GPIO G3 A12 MSIOF1_SS1 SCIFA5_RXD_B GP0_28 3 3V VCCQ 8mA O L O I IO I On 186 LBSC MSIOF1 SCIFA5 I Mode Pin G1 A13 MSIOF1_SS2 SCIFA5_TXD_B GP0_29 3 3V VCCQ 8mA MD6 O L O O IO I Off 187 LBSC MSIOF2 HSCIF0 LBSC I GPIO K5 A14 MSIOF2_RXD HSCIF0_HRX_B DREQ1 GP0...

Page 44: ...ved I GPIO D1 EX_CS2 PWM0 SCIF4_RXD_C TPUTO3 SCIFB2_TXD GP1_14 3 3V VCCQ 4mA O O I O O IO I On 205 LBSC SCIFA2 SCIF4 Reserved Reserved Reserved SCIFB2 Reserved I GPIO D2 EX_CS3 SCIFA2_SCK SCIF4_TXD_C SCIFB2_SCK GP1_15 3 3V VCCQ 8mA O O O O IO I On 206 LBSC SCIFA2 I2C2 Reserved Reserved Reserved SCIFB2 Reserved I GPIO C1 EX_CS4 SCIFA2_RXD I2C2_SCL_E SCIFB2_CTS GP1_16 3 3V VCCQ 4mA O I IO I IO I On ...

Page 45: ... 223 DU0 Reserved I GPIO AC19 DU0_DR7 GP2_7 3 3V VCCQ 8mA O IO I On 224 DU0 Reserved SCIFA0 I2C3 I GPIO AA17 DU0_DG0 SCIFA0_RXD_C I2C3_SCL_D GP2_8 3 3V VCCQ 8mA O I IO IO I On 225 DU0 Reserved SCIFA0 I2C3 I GPIO AB16 DU0_DG1 SCIFA0_TXD_C I2C3_SDA_D GP2_9 3 3V VCCQ 8mA O O IO IO I On 226 DU0 Reserved I GPIO AD18 DU0_DG2 GP2_10 3 3V VCCQ 8mA O IO I On 227 DU0 Reserved I GPIO AD16 DU0_DG3 GP2_11 3 3V...

Page 46: ...V VCCQ 8mA MD11 IO IO I Off 244 DU0 Reserved I Mode Pin AB14 DU0_EXVSYNC DU0_VSYNC GP2_28 3 3V VCCQ 8mA MD12 IO IO I Off 245 DU0 Reserved I GPIO AC13 DU0_EXODDF DU0_ODDF DISP CDE GP2_29 3 3V VCCQ 8mA IO IO I On 246 DU0 Reserved I Mode Pin AE18 DU0_DISP GP2_30 3 3V VCCQ 8mA MD10 O IO I Off 247 DU0 Reserved I Mode Pin AB13 DU0_CDE GP2_31 3 3V VCCQ 8mA MD13 O IO I Off 248 VIN0 EthernetAVB I GPIO AB1 ...

Page 47: ...GP3_17 3 3V VCCQ 8mA I I O I O IO I On 266 EtherMAC VIN0 MSIOF2 SCIF4 EthernetAVB Reserved I GPIO V5 ETH_LINK VI0_G5 MSIOF2_SS2_B SCIF4_TXD_D AVB_TXD4 GP3_18 3 3V VCCQ 8mA I I O O O IO I On 267 EtherMAC VIN0 SCIF2 EthernetAVB SSI I GPIO V1 ETH_REF_CLK VI0_G6 SCIF2_SCK_C AVB_TXD5 SSI_SCK5_B GP3_19 3 3V VCCQ 8mA I I IO O IO IO I On 268 EtherMAC VIN0 SCIF2 IIC0 I2C6 EthernetAVB SSI I GPIO V2 ETH_TXD1...

Page 48: ...ed I GPIO AB25 MSIOF0_SYNC PWM1 DU1_DR5 GP4_5 3 3V VCCQ 8mA IO O O IO I On 286 MSIOF0 SCIFA0 Reserved DU1 Reserved Reserved Reserved I GPIO Y22 MSIOF0_SS1 SCIFA0_RXD DU1_DR6 GP4_6 3 3V VCCQ 8mA O I O IO I On 287 MSIOF0 SCIFA0 Reserved DU1 Reserved Reserved I GPIO W22 MSIOF0_SS2 SCIFA0_TXD DU1_DR7 GP4_7 3 3V VCCQ 8mA O O O IO I On 288 HSCIF1 I2C4 PWM6 DU1 I GPIO AB23 HSCIF1_HRX I2C4_SCL PWM6 DU1_DG...

Page 49: ...6 3 3V VCCQ 8mA IO O IO O IO I On 307 SSI SCIFA1 DU1 I GPIO AE20 SSI_SCK6 SCIFA1_SCK_B DU1_EXHSYNC DU1_HSYNC GP4_27 3 3V VCCQ 8mA IO O IO IO I On 308 SSI SCIFA1 I2C4 DU1 I GPIO AD20 SSI_WS6 SCIFA1_RXD_B I2C4_SCL_C DU1_EXVSYNC DU 1_VSYNC GP4_28 3 3V VCCQ 8mA IO I IO IO IO I On 309 SSI SCIFA1 I2C4 DU1 I GPIO AE21 SSI_SDATA6 SCIFA1_TXD_B I2C4_SDA_C DU1_EXODDF DU1 _ODDF DISP CDE GP4_29 3 3V VCCQ 8mA I...

Page 50: ...A IO I IO I I I IO On 327 SSI SCIF1 IIC0 I2C6 VIN1 RCAN0 Reserved EtherMAC I GPIO AB5 SSI_WS1 SCIF1_TXD_B IIC0_SDA_C VI1_DATA0 CAN0_TX_D ETH_RX_ER_ B GP5_12 3 3V VCCQ 8mA IO O IO I O I IO On 328 SSI HSCIF1 VIN1 Reserved LBSC EtherMAC I GPIO AC5 SSI_SDATA1 HSCIF1_HRX_B VI1_DATA1 ATAWR0 ETH_RXD 0_B GP5_13 3 3V VCCQ 8mA IO I I O I IO On 329 SSI HSCIF1 VIN1 Reserved LBSC EtherMAC I GPIO AE4 SSI_SCK2 H...

Page 51: ...rved EtherMAC I GPIO AE2 AUDIO_CLKB I2C0_SDA_B SCIFA4_TXD_D VI1_FIELD ETH_MDC_B GP5_21 3 3V VCCQ 8mA I IO O I O IO I On 337 ADG I2C4 SCIFA5 VIN1 Reserved Reserved Reserved Reserved I GPIO AC1 AUDIO_CLKC I2C4_SCL_B SCIFA5_RXD_D VI1_HSYNC GP5_22 3 3V VCCQ 8mA I IO I I IO I On 338 ADG I2C4 SCIFA5 VIN1 Reserved Reserved Reserved Reserved I GPIO AC2 AUDIO_CLKOUT I2C4_SDA_B SCIFA5_TXD_D VI1_VSYNC GP5_23...

Page 52: ...ault pull up Internal pull up control function is available or not from a power on reset and its pull up state On Pull up control function is available and default state is pulled up No 110 ACK pin is available internal pull down function Off Pull up control function is available and default state is not pulled up Pull up control function is not available For details of pull up control function re...

Page 53: ...S H 17 E13 M0CAS O H M0CAS H 18 B9 M0A0 O L M0A0 L 19 B12 M0A1 O L M0A1 L 20 A11 M0A2 O L M0A2 L 21 B10 M0A3 O L M0A3 L 22 B13 M0A4 O L M0A4 L 23 B8 M0A5 O L M0A5 L 24 A7 M0A6 O L M0A6 L 25 B14 M0A7 O L M0A7 L 26 D8 M0A8 O L M0A8 L 27 B11 M0A9 O L M0A9 L 28 A8 M0A10 O L M0A10 L 29 A9 M0A11 O L M0A11 L 30 A6 M0A12 O L M0A12 L 31 B7 M0A13 O L M0A13 L 32 D7 M0A14 O L M0A14 L 33 A12 M0A15 O L M0A15 L ...

Page 54: ...2 M0DQ17 IO Z M0DQ17 Z 68 E24 M0DQ18 IO Z M0DQ18 Z 69 C25 M0DQ19 IO Z M0DQ19 Z 70 F24 M0DQ20 IO Z M0DQ20 Z 71 D24 M0DQ21 IO Z M0DQ21 Z 72 B25 M0DQ22 IO Z M0DQ22 Z 73 C24 M0DQ23 IO Z M0DQ23 Z 74 F25 M0DQS2 IO Z 1 M0DQS2 Z 1 75 E25 M0DQS2 IO Z 1 M0DQS2 Z 1 76 F22 M0DM2 O Z M0DM2 Z 77 J21 VDDQ_M0DPLL2 P P 78 H21 VSSQ_M0DPLL2 P P 79 G23 M0VREFDQ1 P P 80 J23 M0DQ24 IO Z M0DQ24 Z 81 K22 M0DQ25 IO Z M0DQ...

Page 55: ... USB0_OVC I I USB0_OVC I 122 N24 USB1_DP IO I USB1_DP I 123 N25 USB1_DM IO I USB1_DM I 124 M24 USB1_RREF P P 125 T21 USB1_PWEN O Z USB1_PWEN L 126 T22 USB1_OVC I I USB1_OVC I 127 R23 NMI I I NMI I 128 AE12 SD0_CLK O I GP6_0 I 129 AD12 SD0_CMD IO I GP6_1 I Off 130 AC11 SD0_DATA0 IO I GP6_2 I Off 131 AD11 SD0_DATA1 IO I GP6_3 I Off 132 AE11 SD0_DATA2 IO I GP6_4 I Off 133 AA12 SD0_DATA3 IO I GP6_5 I ...

Page 56: ..._12 4 I On 170 D5 D13 IO I D13 GP0_13 4 I On 171 D3 D14 IO I D14 GP0_14 4 I On 172 F5 D15 IO I D15 GP0_15 4 I On 173 F4 A0 O I MD3 A0 GP0_16 4 L I Off 174 F3 A1 O I MD0 A1 GP0_17 4 L I Off 175 G4 A2 O I MDT1 A2 GP0_18 4 L I Off 176 H5 A3 O I MD2 A3 GP0_19 4 L I Off 177 H4 A4 O I MD1 A4 GP0_20 4 L I Off 178 F2 A5 O I A5 GP0_21 4 L I On 179 G5 A6 O I A6 GP0_22 4 L I On 180 F1 A7 O I MD4 A7 GP0_23 4 ...

Page 57: ...DR3 O I GP2_3 I On 220 AD19 DU0_DR4 O I GP2_4 I On 221 AD17 DU0_DR5 O I GP2_5 I On 222 AC17 DU0_DR6 O I GP2_6 I On 223 AC19 DU0_DR7 O I GP2_7 I On 224 AA17 DU0_DG0 O I GP2_8 I On 225 AB16 DU0_DG1 O I GP2_9 I On 226 AD18 DU0_DG2 O I GP2_10 I On 227 AD16 DU0_DG3 O I GP2_11 I On 228 AB17 DU0_DG4 O I GP2_12 I On 229 AA16 DU0_DG5 O I GP2_13 I On 230 AE16 DU0_DG6 O I GP2_14 I On 231 AC16 DU0_DG7 O I GP2...

Page 58: ...D1 O I GP3_20 I On 269 U3 ETH_TX_EN O I GP3_21 I On 270 W4 ETH_MAGIC O I GP3_22 I On 271 U2 ETH_TXD0 O I GP3_23 I On 272 W5 ETH_MDC O I GP3_24 I On 273 U1 HSCIF0_HRX I I GP3_25 I On 274 T4 HSCIF0_HTX O I GP3_26 I On 275 T3 HSCIF0_HCTS IO I GP3_27 I On 276 T2 HSCIF0_HRTS IO I GP3_28 I On 277 T1 HSCIF0_HSCK IO I GP3_29 I On 278 Y5 I2C0_SCL IO I GP3_30 I On 279 Y4 I2C0_SDA IO I GP3_31 I On 280 Y24 I2...

Page 59: ...REF IO IO Reserved IO 323 W20 VSS_MLBPLL P P 324 V21 VDD_MLBPLL P P 325 AC6 SSI_SDATA8 IO I GP5_10 I On 326 AE6 SSI_SCK1 IO I GP5_11 I On 327 AB5 SSI_WS1 IO I GP5_12 I On 328 AC5 SSI_SDATA1 IO I GP5_13 I On 329 AE4 SSI_SCK2 IO I GP5_14 I On 330 AD4 SSI_WS2 IO I GP5_15 I On 331 AC4 SSI_SDATA2 IO I GP5_16 I On 332 AE3 SSI_SCK9 IO I GP5_17 I On 333 AD3 SSI_WS9 IO I GP5_18 I On 334 AD2 SSI_SDATA9 IO I...

Page 60: ... 198 200 201 208 209 and 211 to 213 Default pin function MD 3 1 000 LBSC D 15 0 A 25 0 CS0 CS1 A26 BS RD WE 1 0 and EX_WAIT0 MD 3 1 000 GPIO GP0_ 31 0 GP1_ 11 0 19 18 23 21 5 No 201 CS1 A26 Default state MD4 0 area 0 64 Mbyte mode high output MD4 1 area 0 128 Mbyte mode low output ...

Page 61: ... operation LBSC area 0 or QSPI Default pull up Internal pull up control function is available or not from a power on reset and its pull up state On Pull up control function is available and default state is pulled up No 110 ACK pin is available internal pull down function Off Pull up control function is available and default state is not pulled up Pull up control function is not available For deta...

Page 62: ...pen 14 D9 M0ZQ IO Must be used 15 E14 M0WE H Open 16 D16 M0RAS H Open 17 E13 M0CAS H Open 18 B9 M0A0 L Open 19 B12 M0A1 L Open 20 A11 M0A2 L Open 21 B10 M0A3 L Open 22 B13 M0A4 L Open 23 B8 M0A5 L Open 24 A7 M0A6 L Open 25 B14 M0A7 L Open 26 D8 M0A8 L Open 27 B11 M0A9 L Open 28 A8 M0A10 L Open 29 A9 M0A11 L Open 30 A6 M0A12 L Open 31 B7 M0A13 L Open 32 D7 M0A14 L Open 33 A12 M0A15 L Open 34 E12 M0...

Page 63: ... Z Open 67 E22 M0DQ17 Z Open 68 E24 M0DQ18 Z Open 69 C25 M0DQ19 Z Open 70 F24 M0DQ20 Z Open 71 D24 M0DQ21 Z Open 72 B25 M0DQ22 Z Open 73 C24 M0DQ23 Z Open 74 F25 M0DQS2 Z 1 Open 75 E25 M0DQS2 Z 1 Open 76 F22 M0DM2 Z Open 77 J21 VDDQ_M0DPLL2 P Must be used 78 H21 VSSQ_M0DPLL2 P Must be used 79 G23 M0VREFDQ1 P Must be used 80 J23 M0DQ24 Z Open 81 K22 M0DQ25 Z Open 82 H22 M0DQ26 Z Open 83 L22 M0DQ27 ...

Page 64: ...p to VCCQ_SD0 or pulled down to VSS 129 AD12 SD0_CMD I Off Pulled up to VCCQ_SD0 or pulled down to VSS 130 AC11 SD0_DATA0 I Off Pulled up to VCCQ_SD0 or pulled down to VSS 131 AD11 SD0_DATA1 I Off Pulled up to VCCQ_SD0 or pulled down to VSS 132 AE11 SD0_DATA2 I Off Pulled up to VCCQ_SD0 or pulled down to VSS 133 AA12 SD0_DATA3 I Off Pulled up to VCCQ_SD0 or pulled down to VSS 134 AB12 SD0_CD I Off...

Page 65: ... 168 B3 D11 I Area 0 On Open 169 A2 D12 I Area 0 On Open 170 D5 D13 I Area 0 On Open 171 D3 D14 I Area 0 On Open 172 F5 D15 I Area 0 On Open 173 F4 A0 L I MD3 Area 0 Off Pulled up to VCCQ or pulled down to VSS 174 F3 A1 L I MD0 Area 0 Off Pulled up to VCCQ or pulled down to VSS 175 G4 A2 L I MDT1 Area 0 Off Pulled up to VCCQ or pulled down to VSS 176 H5 A3 L I MD2 Area 0 Off Pulled up to VCCQ or p...

Page 66: ...214 L5 DREQ0 I On Open 215 M2 DACK0 I MD21 Off Pulled up to VCCQ or pulled down to VSS 216 AA18 DU0_DR0 I On Open 217 AB18 DU0_DR1 I On Open 218 AE19 DU0_DR2 I On Open 219 AC18 DU0_DR3 I On Open 220 AD19 DU0_DR4 I On Open 221 AD17 DU0_DR5 I On Open 222 AC17 DU0_DR6 I On Open 223 AC19 DU0_DR7 I On Open 224 AA17 DU0_DG0 I On Open 225 AB16 DU0_DG1 I On Open 226 AD18 DU0_DG2 I On Open 227 AD16 DU0_DG3...

Page 67: ...W1 VI0_VSYNC I On Open 261 T5 ETH_MDIO I On Open 262 V4 ETH_CRS_DV I On Open 263 U5 ETH_RX_ER I On Open 264 V3 ETH_RXD0 I On Open 265 U4 ETH_RXD1 I On Open 266 V5 ETH_LINK I On Open 267 V1 ETH_REF_CLK I On Open 268 V2 ETH_TXD1 I On Open 269 U3 ETH_TX_EN I On Open 270 W4 ETH_MAGIC I On Open 271 U2 ETH_TXD0 I On Open 272 W5 ETH_MDC I On Open 273 U1 HSCIF0_HRX I On Open 274 T4 HSCIF0_HTX I On Open 27...

Page 68: ...TA7 I On Open 313 AE5 SSI_SCK0129 I On Open 314 AA7 SSI_WS0129 I On Open 315 AA6 SSI_SDATA0 I On Open 316 AD6 SSI_SCK34 I On Open 317 AB6 SSI_WS34 I On Open 318 AD5 SSI_SDATA3 I On Open 319 AD22 SSI_SCK4 I Pulled up to VCCQ or pulled down to VSS 320 AB21 SSI_WS4 I Pulled up to VCCQ or pulled down to VSS 321 Y21 SSI_SDATA4 I Pulled up to VCCQ or pulled down to VSS 322 AD24 MLB_REF IO Open 323 W20 V...

Page 69: ... low level for the M0DQSx pin and high level for the M0DQSx pin respectively 2 No 137 to 142 and 146 to 151 Default pin function and pin state Depends on MD 21 20 MD 12 10 and MDT 1 0 settings I is in function mode GPIO Z is in debug mode 3 No 138 to 142 and 147 to 151 Default pull up is in debugging operation only Off is in other than debugging operation 4 No 201 CS1 A26 Default state MD4 0 area ...

Page 70: ...3 Module selection Enable and disable the functions of RZ G1E LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module Selection is handled by the module select register MOD_SEL module select register 2 MOD_SEL2 and module select register 3 MOD_SEL3 For details see sections 5 3 23 Module Select Register MOD_SEL through 5 3 25 Module Select Re...

Page 71: ...n select register 3 GPSR3 R W H 0000 0000 H E606 0010 32 GPIO peripheral function select register 4 GPSR4 R W H 0000 0000 H E606 0014 32 GPIO peripheral function select register 5 GPSR5 R W H 0F00 0000 H E606 0018 32 GPIO peripheral function select register 6 GPSR6 R W H 0000 0000 H E606 001C 32 Peripheral function select register 0 IPSR0 R W H 0000 0000 H E606 0020 32 Peripheral function select r...

Page 72: ...8 32 LSI pin pull up control register 0 PUPR0 R W H 5D60 FFFF H E606 0100 32 LSI pin pull up control register 1 PUPR1 R W H 7FD8 3FF3 H E606 0104 32 LSI pin pull up control register 2 PUPR2 R W H 27FF FFFF H E606 0108 32 LSI pin pull up control register 3 PUPR3 R W H FFFF FFFF H E606 010C 32 LSI pin pull up control register 4 PUPR4 R W H FFFF FFFF H E606 0110 32 LSI pin pull up control register 5 ...

Page 73: ...0 Readable writable Writing 0 initializes the bit Writing 1 is ignored R WC1 Readable writable Writing 1 initializes the bit Writing 0 is ignored W Write only Reading this bit is prohibited When the bit is reserved the write value should always be 0 W Write only The read value is undefined All the bits are active high unless otherwise specified and deactivated on reset All access to registers is m...

Page 74: ...heral Function Select Register 0 GPSR0 Function GPSR0 selects the functions of the multiplexed LSI pins Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP0 31 GP0 30 GP0 29 GP0 28 GP0 27 GP0 26 GP0 25 GP0 24 GP0 23 GP0 22 GP0 21 GP0 20 GP0 19 GP0 18 GP0 17 GP0 16 Initial value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R ...

Page 75: ...IP1 14 13 GP0 13 GP 0 13 peripheral function selected by IP1 17 15 GP0 14 GP 0 14 peripheral function selected by IP1 19 18 GP0 15 GP 0 15 peripheral function selected by IP1 21 20 GP0 16 GP 0 16 peripheral function selected by IP1 23 22 GP0 17 GP 0 17 peripheral function selected by IP1 24 GP0 18 GP 0 18 A2 GP0 19 GP 0 19 peripheral function selected by IP1 26 GP0 20 GP 0 20 peripheral function s...

Page 76: ...ediately before setting this register Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP1 0 GP 1 0 Peripheral function selected by IP2 20 18 GP1 1 GP 1 1 Peripheral function selected by IP2 23 21 GP1 2 GP 1 2 Peripheral function selected by IP2 26 24 GP1 3 GP 1 3 Peripheral function selected by IP2 29 27 GP1 4 GP 1 4 Peripheral function selected by IP2 31 30 GP1 5 GP 1 5 Peripheral funct...

Page 77: ... 8 Sep 30 2016 Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP1 22 GP 1 22 WE1_N GP1 23 GP 1 23 Peripheral function selected by IP4 1 0 GP1 24 GP 1 24 Peripheral function selected by IP7 31 GP1 25 GP 1 25 DACK0 GP1 26 GP1 27 GP1 28 GP1 29 GP1 30 GP1 31 ...

Page 78: ...2 GP2 1 GP 2 1 Peripheral function selected by IP4 7 5 GP2 2 GP 2 2 Peripheral function selected by IP4 9 8 GP2 3 GP 2 3 Peripheral function selected by IP4 11 10 GP2 4 GP 2 4 Peripheral function selected by IP4 13 12 GP2 5 GP 2 5 Peripheral function selected by IP4 15 14 GP2 6 GP 2 6 Peripheral function selected by IP4 17 16 GP2 7 GP 2 7 Peripheral function selected by IP4 19 18 GP2 8 GP 2 8 Peri...

Page 79: ...function selected by IP5 27 26 GP2 26 GP 2 26 Peripheral function selected by IP5 29 28 GP2 27 GP 2 27 Peripheral function selected by IP5 31 30 GP2 28 GP 2 28 Peripheral function selected by IP6 1 0 GP2 29 GP 2 29 Peripheral function selected by IP6 3 2 GP2 30 GP 2 30 Peripheral function selected by IP6 5 4 GP2 31 GP 2 31 Peripheral function selected by IP6 7 6 ...

Page 80: ...ed by IP6 8 GP3 1 GP 3 1 Peripheral function selected by IP6 9 GP3 2 GP 3 2 Peripheral function selected by IP6 10 GP3 3 GP 3 3 Peripheral function selected by IP6 11 GP3 4 GP 3 4 Peripheral function selected by IP6 12 GP3 5 GP 3 5 Peripheral function selected by IP6 13 GP3 6 GP 3 6 Peripheral function selected by IP6 14 GP3 7 GP 3 7 Peripheral function selected by IP6 15 GP3 8 GP 3 8 Peripheral f...

Page 81: ...unction selected by IP8 5 3 GP3 26 GP 3 26 Peripheral function selected by IP8 8 6 GP3 27 GP 3 27 Peripheral function selected by IP8 11 9 GP3 28 GP 3 28 Peripheral function selected by IP8 14 12 GP3 29 GP 3 29 Peripheral function selected by IP8 16 15 GP3 30 GP 3 30 Peripheral function selected by IP8 19 17 GP3 31 GP 3 31 Peripheral function selected by IP8 22 20 ...

Page 82: ...4 1 GP 4 1 Peripheral function selected by IP8 28 26 GP4 2 GP 4 2 Peripheral function selected by IP8 31 29 GP4 3 GP 4 3 Peripheral function selected by IP9 2 0 GP4 4 GP 4 4 Peripheral function selected by IP9 5 3 GP4 5 GP 4 5 Peripheral function selected by IP9 8 6 GP4 6 GP 4 6 Peripheral function selected by IP9 11 9 GP4 7 GP 4 7 Peripheral function selected by IP9 14 12 GP4 8 GP 4 8 Peripheral ...

Page 83: ...tion selected by IP11 2 0 GP4 26 GP 4 26 Peripheral function selected by IP11 5 3 GP4 27 GP 4 27 Peripheral function selected by IP11 7 6 GP4 28 GP 4 28 Peripheral function selected by IP11 10 8 GP4 29 GP 4 29 Peripheral function selected by IP11 13 11 GP4 30 GP 4 30 Peripheral function selected by IP11 15 14 GP4 31 GP 4 31 Peripheral function selected by IP11 17 16 ...

Page 84: ...11 20 18 GP5 1 GP 5 1 Peripheral function selected by IP11 23 21 GP5 2 GP 5 2 Peripheral function selected by IP11 26 24 GP5 3 GP 5 3 Peripheral function selected by IP11 29 27 GP5 4 GP 5 4 Peripheral function selected by IP12 2 0 GP5 5 GP 5 5 Peripheral function selected by IP12 5 3 GP5 6 GP 5 6 Peripheral function selected by IP12 8 6 GP5 7 GP 5 7 Peripheral function selected by IP12 10 9 GP5 8 ...

Page 85: ...ion Controller PFC R01UH0544EJ0100 Rev 1 00 5 16 Sep 30 2016 Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP5 25 GP 5 25 USB0_OVC GP5 26 GP 5 26 USB1_PWEN GP5 27 GP 5 27 USB1_OVC GP5 28 GP5 29 GP5 30 GP5 31 ...

Page 86: ...this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP6 0 GP 6 0 SD0_CLK GP6 1 GP 6 1 SD0_CMD GP6 2 GP 6 2 SD0_DATA0 GP6 3 GP 6 3 SD0_DATA1 GP6 4 GP 6 4 SD0_DATA2 GP6 5 GP 6 5 SD0_DATA3 GP6 6 GP 6 6 SD0_CD GP6 7 GP 6 7 SD0_WP GP6 8 GP 6 8 SD1_CLK GP6 9 GP 6 9 SD1_...

Page 87: ...tion Controller PFC R01UH0544EJ0100 Rev 1 00 5 18 Sep 30 2016 Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP6 25 GP 6 25 Peripheral function selected by IP0 21 20 GP6 26 GP6 27 GP6 28 GP6 29 GP6 30 GP6 31 ...

Page 88: ... 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5...

Page 89: ...I pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Others Set Value H 7 t...

Page 90: ... to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 Others Set Value H 8 to H ...

Page 91: ...ppropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 Others Set Value H 8 to H F IP3 1 0 A21 MOSI_IO0 Reserved IP3 3 2 A22 MISO_IO1 Reserve...

Page 92: ... LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Others Set Value H 6 to H F IP4 1 0 EX_WAIT0...

Page 93: ...lected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Others Set Value H 6 to H F IP5 1 0 DU0_DG5 Reserved Reserve...

Page 94: ...the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Others Set Value H 7 to H F IP6 1 0 DU0_EXVSYNC_DU0_ VSYNC Reserved Reserved IP6 3 2 DU0_EXODDF_DU0_ ODDF_DISP_CDE Reserved Rese...

Page 95: ...o enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 IP7 2 0 ETH_CRS_DV VI0_G1 MSIOF2_TXD_B I2C5_SDA_D AVB_TXD0 Reserved Reserved ...

Page 96: ...y set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 IP8 2 0 ETH_MDC VI0_R3 SCIF3_TXD_B I2C4_SDA_E AVB_MDC SSI_SDATA6_B IP8 5 3 HSCIF0_HRX VI0_R4 I2C1...

Page 97: ...o be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 IP9 2 0 MSIOF0_TXD SCIF5_TXD I2C2_SDA_C DU1_DR3 Reserved Reserved Reserved R...

Page 98: ...opriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 IP10 2 0 SCIF1_RXD I2C5_SCL DU1_DG6 SSI_SCK2_B Reserved Reserved IP10 5 3 SCIF1_TXD I2C5_...

Page 99: ...g to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 IP11 2 0 SSI_WS5 SCIFA3_RXD I2C3_SCL_C DU1_DOTCLKOUT0 Reserved IP11 5 3 SSI...

Page 100: ... Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 IP12 2 0 SSI_SCK34 MSIOF1_SYNC_B SCIFA1_SCK_C Reserved Reserved DREQ1_...

Page 101: ... to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 IP13 2 0 SSI_WS2 HSCIF1_HCTS_ N_B SCIFA0_RXD_D VI1_DATA3 Reserved ATACS00_...

Page 102: ...10 IP1 10 8 GP0 11 D11 HSCIF2_HCTS_ N SCIF1_RXD_C I2C1_SCL_D GP0 11 IP1 12 11 GP0 12 D12 HSCIF2_HRTS_ N SCIF1_TXD_C I2C1_SDA_D GP0 12 IP1 14 13 GP0 13 D13 SCIFA1_SCK Reserved PWM2_C TCLK2_B GP0 13 IP1 17 15 GP0 14 D14 SCIFA1_RXD I2C5_SCL_B GP0 14 IP1 19 18 GP0 15 D15 SCIFA1_TXD I2C5_SDA_B GP0 15 IP1 21 20 GP0 16 A0 SCIFB1_SCK PWM3_B GP0 16 IP1 23 22 GP0 17 A1 SCIFB1_TXD GP0 17 IP1 24 GP0 18 A2 GP0...

Page 103: ...CK0 PWM1_C TPUTO0_C ATACS01_N Reserved GP1 18 IP3 29 27 GP1 19 RD_N ATACS11_N GP1 19 IP3 30 GP1 20 RD_WR_N ATAG1_N GP1 20 IP3 31 GP1 21 WE0_N GP1 21 GP1 22 WE1_N GP1 22 GP1 23 EX_WAIT0 CAN_CLK_B SCIF_CLK Reserved GP1 23 IP4 1 0 GP1 24 DREQ0_N SCIFB1_RXD GP1 24 IP7 31 GP1 25 DACK0 GP1 25 GP2 0 DU0_DR0 Reserved SCIF5_RXD_C I2C2_SCL_D Reserved GP2 0 IP4 4 2 GP2 1 DU0_DR1 Reserved SCIF5_TXD_C I2C2_SDA...

Page 104: ...31 IP6 7 6 GP3 0 VI0_CLK AVB_RX_CLK GP3 0 IP6 8 GP3 1 VI0_DATA0_VI0_ B0 AVB_RX_DV GP3 1 IP6 9 GP3 2 VI0_DATA1_VI0_ B1 AVB_RXD0 GP3 2 IP6 10 GP3 3 VI0_DATA2_VI0_ B2 AVB_RXD1 GP3 3 IP6 11 GP3 4 VI0_DATA3_VI0_ B3 AVB_RXD2 GP3 4 IP6 12 GP3 5 VI0_DATA4_VI0_ B4 AVB_RXD3 GP3 5 IP6 13 GP3 6 VI0_DATA5_VI0_ B5 AVB_RXD4 GP3 6 IP6 14 GP3 7 VI0_DATA6_VI0_ B6 AVB_RXD5 GP3 7 IP6 15 GP3 8 VI0_DATA7_VI0_ B7 AVB_RX...

Page 105: ...M5_B DU1_DR0 Reserved Reserved TPUTO1_B GP4 0 IP8 25 23 GP4 1 I2C1_SDA SCIF4_TXD IRQ5 DU1_DR1 Reserved Reserved Reserved GP4 1 IP8 28 26 GP4 2 MSIOF0_ RXD SCIF5_RXD I2C2_SCL_C DU1_DR2 Reserved Reserved Reserved Reserved GP4 2 IP8 31 29 GP4 3 MSIOF0_ TXD SCIF5_TXD I2C2_SDA_C DU1_DR3 Reserved Reserved Reserved Reserved GP4 3 IP9 2 0 GP4 4 MSIOF0_ SCK IRQ0 Reserved DU1_DR4 Reserved TPUTO1_C GP4 4 IP9...

Page 106: ...IP11 26 24 GP5 3 SSI_SDATA0 MSIOF1_SCK_B PWM0_B Reserved Reserved GP5 3 IP11 29 27 GP5 4 SSI_SCK34 MSIOF1_SYNC_ B SCIFA1_SCK_C Reserved Reserved DREQ1_N_B GP5 4 IP12 2 0 GP5 5 SSI_WS34 MSIOF1_SS1_B SCIFA1_RXD_C Reserved CAN1_RX_C DACK1_B GP5 5 IP12 5 3 GP5 6 SSI_SDATA3 MSIOF1_SS2_B SCIFA1_TXD_C Reserved CAN1_TX_C DREQ2_N GP5 6 IP12 8 6 GP5 7 SSI_SCK4 Reserved Reserved Reserved GP5 7 IP12 10 9 GP5 ...

Page 107: ...B1_OVC GP5 27 GP6 0 SD0_CLK GP6 0 GP6 1 SD0_CMD GP6 1 GP6 2 SD0_DATA0 GP6 2 GP6 3 SD0_DATA1 GP6 3 GP6 4 SD0_DATA2 GP6 4 GP6 5 SD0_DATA3 GP6 5 GP6 6 SD0_CD GP6 6 GP6 7 SD0_WP GP6 7 GP6 8 SD1_CLK GP6 8 GP6 9 SD1_CMD GP6 9 GP6 10 SD1_DATA0 GP6 10 GP6 11 SD1_DATA1 GP6 11 GP6 12 SD1_DATA2 GP6 12 GP6 13 SD1_DATA3 GP6 13 GP6 14 SD1_CD CAN0_RX GP6 14 IP0 0 GP6 15 SD1_WP IRQ7 CAN0_TX GP6 15 IP0 9 8 GP6 16 ...

Page 108: ... W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sel_i2c 00 0 sel_i2c 01 2 sel_i2c 01 1 sel_i2c 01 0 sel_i2c 02 2 sel_i2c 02 1 sel_i2c 02 0 sel_i2c 03 2 sel_i2c 03 1 sel_i2c 03 0 sel_i2c 04 2 sel_i2c 04 1 sel_i2c 04 0 sel_i2c 05 1 sel_i2c 05 0 sel_avb 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Init...

Page 109: ...D8 for function I2C1_SCL_B select pin D9 for function I2C1_SDA_B select pin HSCIF0_HRX for function I2C1_SCL_C select pin HSCIF0_HTX for function I2C1_SDA_C select pin D11 for function I2C1_SCL_D select pin D12 for function I2C1_SDA_D select pin SCIF3_RXD for function I2C1_SCL_E select pin SCIF3_TXD for function I2C1_SDA_E sel_i2c02 2 0 select pin I2C2_SCL for function I2C2_SCL select pin I2C2_SDA...

Page 110: ...el_scif a4 1 sel_scif a4 0 sel_scif a5 1 sel_scif a5 0 sel_tmu 0 sel_can 0 1 sel_can 0 0 sel_can 1 1 sel_can 1 0 sel_hsc if0 0 sel_hsc if1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W These bits select multiplexed pin functions as indicated in the table below Note To ena...

Page 111: ...S4_N for function SCIFA2_RXD select pin EX_CS5_N for function SCIFA2_TXD select pin SSI_SCK78 for function SCIFA2_SCK_B select pin SSI_SDATA7 for function SCIFA2_TXD_B select pin SSI_WS78 for function SCIFA2_RXD_B sel_scifa3 0 select pin SSI_SCK5 for function SCIFA3_SCK select pin SSI_SDATA5 for function SCIFA3_TXD select pin SSI_WS5 for function SCIFA3_RXD select pin D0 for function SCIFA3_SCK_B ...

Page 112: ...n 5 Set Value H 4 sel_hscif1 0 select pin HSCIF1_HCTS_N for function HCTS1_N select pin HSCIF1_HRTS_N for function HRTS1_N select pin HSCIF1_HRX for function HRX1 select pin HSCIF1_HTX for function HTX1 select pin SSI_SCK2 for function HTX1_B select pin SSI_SDATA1 for function HRX1_B select pin SSI_SDATA2 for function HRTS1_N_B select pin SSI_WS2 for function HCTS1_N_B Legend Setting prohibited ...

Page 113: ...tting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 sel_scif0 1 0 select pin EX_WAIT0 for function SCIF_CLK select pin MMC_D6 for function SCIF0_RXD select pin MMC_D7 for function SCIF0_TX0 select pin HSCIF0_HSCK for function SCIF_CLK_B select pin VI0_HSYNC_N for function SCIF0_RXD_B select pin VI...

Page 114: ...I_SDATA4 select pin SSI_WS4 for function SSI_WS4 select pin I2C2_SCL for function SSI_SDATA4_B select pin SCIF3_RXD for function SSI_SCK4_B select pin SCIF3_TXD for function SSI_WS4_B sel_ssi5 0 select pin SSI_SCK5 for function SSI_SCK5 select pin SSI_SDATA5 for function SSI_SDATA5 select pin SSI_WS5 for function SSI_WS5 select pin ETH_REF_CLK for function SSI_SCK5_B select pin ETH_TXD1 for functi...

Page 115: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR0 31 0 H 5D60 FFFF R W Performs individual on off control of the pull up down resistor provided in each signal pin of the LSI 0 Pull up down function is disabled 1 Pull up down function is enabled Bit Name Set Value 1 PUPR0 31 A15 is pull up PUPR0 30 A14 is pull up PUPR0 29 A1...

Page 116: ...roller PFC R01UH0544EJ0100 Rev 1 00 5 47 Sep 30 2016 Bit Name Set Value 1 PUPR0 6 D6 is pull up PUPR0 5 D5 is pull up PUPR0 4 D4 is pull up PUPR0 3 D3 is pull up PUPR0 2 D2 is pull up PUPR0 1 D1 is pull up PUPR0 0 D0 is pull up ...

Page 117: ... R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR1 31 0 H 7FD8 3FF3 R W Performs individual on off control of the pull up down resistor provided in each signal pin of the LSI 0 Pull up down function is disabled 1 Pull up down function is enabled Bit Name Set Value 1 PUPR1 31 PUPR1 30 ACK is pull down PUPR1 29 EX_CS5_N is pull up PUPR1 28 EX_CS3_N is pull ...

Page 118: ...ler PFC R01UH0544EJ0100 Rev 1 00 5 49 Sep 30 2016 Bit Name Set Value 1 PUPR1 6 A22 is pull up PUPR1 5 A21 is pull up PUPR1 4 A20 is pull up PUPR1 3 A19 is pull up PUPR1 2 A18 is pull up PUPR1 1 A17 is pull up PUPR1 0 A16 is pull up ...

Page 119: ...lue R W Description 31 to 0 PUPR2 31 0 H 27FF FFFF R W Performs individual on off control of the pull up down resistor provided in each signal pin of the LSI 0 Pull up down function is disabled 1 Pull up down function is enabled Bit Name Set Value 1 PUPR2 31 DU0_CDE is pull up PUPR2 30 DU0_DISP is pull up PUPR2 29 DU0_EXODDF_DU0_ODDF_DISP_CDE is pull up PUPR2 28 DU0_EXVSYNC_DU0_VSYNC is pull up PU...

Page 120: ...544EJ0100 Rev 1 00 5 51 Sep 30 2016 Bit Name Set Value 1 PUPR2 6 DU0_DR6 is pull up PUPR2 5 DU0_DR5 is pull up PUPR2 4 DU0_DR4 is pull up PUPR2 3 DU0_DR3 is pull up PUPR2 2 DU0_DR2 is pull up PUPR2 1 DU0_DR1 is pull up PUPR2 0 DU0_DR0 is pull up ...

Page 121: ... Initial Value R W Description 31 to 0 PUPR3 31 0 H FFFF FFFF R W Performs individual on off control of the pull up down resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR3 31 I2C1_SDA is pull up PUPR3 30 I2C1_SCL is pull up PUPR3 29 I2C0_SDA is pull up PUPR3 28 I2C0_SCL is pull up PUPR3 27 HSCIF0_HSCK is pull up P...

Page 122: ...016 Bit Name Set Value 1 PUPR3 6 VI0_DATA7_VI0_B7 is pull up PUPR3 5 VI0_DATA6_VI0_B6 is pull up PUPR3 4 VI0_DATA5_VI0_B5 is pull up PUPR3 3 VI0_DATA4_VI0_B4 is pull up PUPR3 2 VI0_DATA3_VI0_B3 is pull up PUPR3 1 VI0_DATA2_VI0_B2 is pull up PUPR3 0 VI0_DATA1_VI0_B1 is pull up ...

Page 123: ...ame Initial Value R W Description 31 to 0 PUPR4 31 0 H FFFF FFFF R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR4 31 SSI_SCK0129 is pull up PUPR4 30 SSI_SDATA7 is pull up PUPR4 29 SSI_WS78 is pull up PUPR4 28 SSI_SCK78 is pull up PUPR4 27 SSI_SDATA6 is pull u...

Page 124: ...ev 1 00 5 55 Sep 30 2016 Bit Name Set Value 1 PUPR4 6 HSCIF1_HRX is pull up PUPR4 5 MSIOF0_SS2 is pull up PUPR4 4 MSIOF0_SS1 is pull up PUPR4 3 MSIOF0_SYNC is pull up PUPR4 2 MSIOF0_SCK is pull up PUPR4 1 MSIOF0_TXD is pull up PUPR4 0 MSIOF0_RXD is pull up ...

Page 125: ...1 0 0 0 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR5 31 0 H 00FF FF1F R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR5 31 PUPR5 30 PUPR5 29 PUPR5 28 PUPR5 27 PUPR5 26 PU...

Page 126: ...er PFC R01UH0544EJ0100 Rev 1 00 5 57 Sep 30 2016 Bit Name Set Value 1 PUPR5 6 PUPR5 5 PUPR5 4 SSI_SDATA3 is pull up PUPR5 3 SSI_WS34 is pull up PUPR5 2 SSI_SCK34 is pull up PUPR5 1 SSI_SDATA0 is pull up PUPR5 0 SSI_WS0129 is pull up ...

Page 127: ...value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR6 31 0 H 0000 0000 R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR6 31 PUPR6 30 PUPR6 29 PUPR6 28 ...

Page 128: ...EJ0100 Rev 1 00 5 59 Sep 30 2016 Bit Name Set Value 1 PUPR6 6 SD0_WP is pull up PUPR6 5 SD0_CD is pull up PUPR6 4 SD0_DATA3 is pull up PUPR6 3 SD0_DATA2 is pull up PUPR6 2 SD0_DATA1 is pull up PUPR6 1 SD0_DATA0 is pull up PUPR6 0 SD0_CMD is pull up ...

Page 129: ...drv2_mmccmd 1 R W MMC_CMD Setting The value of these bits must be 11 28 drv1_mmccmd 1 R W 27 drv2_mmcd0 1 R W MMC_CD0 Setting The value of these bits must be 11 26 drv1_mmcd0 1 R W 25 drv2_mmcd1 1 R W MMC_CD1 Setting The value of these bits must be 11 24 drv1_mmcd1 1 R W 23 drv2_mmcd2 1 R W MMC_CD2 Setting The value of these bits must be 11 22 drv1_mmcd2 1 R W 21 drv2_mmcd3 1 R W MMC_CD3 Setting T...

Page 130: ...t Bit Name Initial Value R W Description 1 drv2_sd0data2 1 R W SD0_DATA2 Setting The value of these bits must be 11 0 drv1_sd0data2 1 R W Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register ...

Page 131: ... The value of these bits must be 11 30 drv1_sd0data3 1 R W 29 drv2_sd0wp 1 R W SD0_WP Setting The value of these bits must be 11 28 drv1_sd0wp 1 R W 27 drv2_sd1cd 1 R W SD1_CD Setting The value of these bits must be 11 26 drv1_sd1cd 1 R W 25 drv2_sd1clk 1 R W SD1_CLK Setting The value of these bits must be 11 24 drv1_sd1clk 1 R W 23 drv2_sd1cmd 1 R W SD1_CMD Setting The value of these bits must be...

Page 132: ...1_a16 0 R W A16 Setting The value of these bits must be 00 28 tdsel0_a16 0 R W 27 tdsel1_audioclkb 0 R W AUDIO_CLKB Setting The value of these bits must be 00 26 tdsel0_audioclkb 0 R W 25 tdsel1_ethrxer 0 R W ETH_RX_ER Setting The value of these bits must be 00 24 tdsel0_ethrxer 0 R W 23 tdsel1_excs3n 0 R W EX_CS3_N Setting The value of these bits must be 00 22 tdsel0_excs3n 0 R W 21 tdsel1_i2c1sd...

Page 133: ...can only be set for the SDHI SDR50 SDR104 mode and the GPIO multiplexed with the SDHI that can be used either 3 3 V or 1 8 V Note that the MMC IO can only be used with 3 3 V 30 poc_mmccmd sd2cmd 1 R W 29 poc_mmcd0 sd2data0 1 R W 28 poc_mmcd1 sd2data1 1 R W 27 poc_mmcd2 sd2data2 1 R W 26 poc_mmcd3 sd2data3 1 R W 25 poc_mmcd4 sd2cd 1 R W 24 poc_mmcd5 sd2wp 1 R W 23 poc_sd0cd 1 R W Selecting IO volta...

Page 134: ... the VCCQ_ MMC _SDn power supply voltage is 3 3 V to use the SDHI inter face as default mode high speed mode or other module function specify 3 3 V for IOCTRL3 then IO voltage of the SDHI channel n and multiplexed other function pins is all 3 3 V In this condition output level of the pin is 3 3 V and if the external device can only operate with1 8 V the external device may be permanently damaged e...

Page 135: ...W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 13 All 0 R W 12 gpreg_msel03_p 15 0 R W Debug monitor function 0 Use DU pins for debug monitor function 1 Use SDHI pins for debug monitor function 11 to 8 All 0 R W 7 conta_iicdvfs 0 R W Control TOF value of IICDVFS IO cell TOF Output fall t...

Page 136: ...et either earlier or later than setting IPSR0 to IPSR13 registers 1 Procedure for changing pin function from GPIO to peripheral function Set the LSI multiplexed pin setting mask register Set the LSI multiplexed pin setting mask register Set the GPIO peripheral function select register GP to peripheral function Set the peripheral function select register IP Clock CPφ Legend GP GPIO peripheral funct...

Page 137: ...heral function after change Peripheral function before change Set value after change Set value before change 1 IP Set the LSI multiplexed pin setting mask register Set the GPIO peripheral function select register GP to peripheral function Legend GP GPIO peripheral function select register bit IP Peripheral function select register bit 1 Figure 5 3 Procedure for Changing Pin Function from One Perip...

Page 138: ...16 Main Revisions and Additions in this Edition Minor revisions such as corrections of errors in spelling and modifications of wording are not included in the revision history Rev Description Page Contents Summary 1 00 First edition issued ...

Page 139: ...RZ G1E User s Manual Hardware Publication Date Rev 1 00 Sep 30 2016 Published by Renesas Electronics Corporation ...

Page 140: ...l 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 SALES OFFICES http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 9251 Yonge Street Suite 8309 Richmond Hill Ontario Canada L4C 9T3 Tel 1 905 237 2004 ...

Page 141: ...RZ G1E R01UH0544EJ0100 ...

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