RZ/G1E
5. Pin Function Controller (PFC)
R01UH0544EJ0100 Rev.1.00
5-41
Sep 30,2016
5.3.24
Module Select Register 2 (MOD_SEL2)
Function: MOD_SEL2 selects the group for multiple LSI pins with multiplexed pin functions.
Each input or input/output signal of the IIC, LBS, MSI, RAD, SCIF, TMU, CAN and HSCIF is assigned to two or more
groups of pins. Select one of these groups when using these signals. Do not use the module pins in the unselected group;
if a module pin in the unselected group is used, correct operation is not guaranteed.
For some modules, however, although the output signals are assigned to two or more groups of pins, there is no bit for
selecting the group. Select one of these pins for each output signal through the corresponding peripheral function select
register. Also note that each pin can only be used in combination with the other input or input/output pins of the same
group. When ssi8 and ssi7 (in MOD_SEL3 register) are to be used simultaneously, the values of sel_ssi8[0] and
sel_ssi7[0] must be the same so that the selected pins belong to the same group. Correct operation is not guaranteed when
a pin is used in combination with pins from other groups.
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— —
sel_iic0
[1]
sel_iic0
[0]
sel_lbs
[0]
sel_msi
1[0]
sel_msi
2[0]
sel_rad
[0]
— —
sel_scif
a0[1]
sel_scif
a0[0]
sel_scif
a1[1]
sel_scif
a1[0]
sel_scif
a2[0]
sel_scif
a3[0]
Initial
value:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W:
R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W R/W
R/W
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sel_scif
a4[1]
sel_scif
a4[0]
sel_scif
a5[1]
sel_scif
a5[0]
—
sel_tmu
[0]
— —
sel_can
0[1]
sel_can
0[0]
sel_can
1[1]
sel_can
1[0]
sel_hsc
if0[0]
sel_hsc
if1[0]
— —
Initial
value:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W:
R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W R/W
R/W
Bit Initial
Value
R/W
Description
31 to 0
H'0000 0000
R/W
These bits select multiplexed pin functions as indicated in the table
below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value = H'0)
Function 2
(Set Value = H'1)
Function 3
(Set Value = H'2)
Function 4
(Set Value = H'3)
Function 5
(Set Value = H'4)
sel_iic0[1:0]
+ select pin SCIF2_RXD for
function IIC0_SCL + select pin
SCIF2_TXD for function
IIC0_SDA
+ select pin A10 for function
IIC0_SCL_B + select pin A11
for function IIC0_SDA_B
+ select pin SSI_SCK1 for
function IIC0_SCL_C + select
pin SSI_WS1 for function
IIC0_SDA_C
+ select pin ETH_TXD1 for
function IIC0_SCL_D + select
pin ETH_TX_EN for function
IIC0_SDA_D
sel_lbs[0]
+ select pin A14 for function
DREQ1_N + select pin A15 for
function DACK1
+ select pin SSI_SCK34 for
function DREQ1_N_B + select
pin SSI_WS34 for function
DACK1_B
sel_msi1[0]
+ select pin A10 for function
MSIOF1_SCK + select pin A11
for function MSIOF1_SYNC +
select pin A12 for function
MSIOF1_SS1 + select pin A13
for function MSIOF1_SS2 +
select pin A8 for function
MSIOF1_RXD + select pin A9
for function MSIOF1_TXD
+ select pin SSI_SCK0129 for
function MSIOF1_RXD_B +
select pin SSI_SCK34 for
function MSIOF1_SYNC_B +
select pin SSI_SDATA0 for
function MSIOF1_SCK_B +
select pin SSI_SDATA3 for
function MSIOF1_SS2_B +
select pin SSI_WS0129 for
function MSIOF1_TXD_B +
select pin SSI_WS34 for
function MSIOF1_SS1_B
Summary of Contents for RZ/G1E
Page 141: ...RZ G1E R01UH0544EJ0100 ...
