Renesas RZ/G1E, User Manual

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RZ/G1E 5. Pin Function Controller (PFC)
R01UH0544EJ0100 Rev.1.00 5-39
Sep 30,2016
5.3.23 Module Select Register (MOD_SEL)
Function: MOD_SEL selects the group for multiple LSI pins with multiplexed pin functions.
Each input or input/output signal of the ADG, ADI, CAN, DR, I2C and AVB an is assigned to two or more groups of
pins. Select one of these groups when using these signals. Do not use the module pins in the unselected group; if a
module pin in the unselected group is used, correct operation is not guaranteed.
For some modules, however, although the output signals are assigned to two or more groups of pins, there is no bit for
selecting the group. Select one of these pins for each output signal through the corresponding peripheral function select
register. Also note that each pin can only be used in combination with the other input or input/output pins of the same
group. Correct operation is not guaranteed when a pin is used in combination with pins from other groups. When ssi7 and
ssi8 (in MOD_SEL3 register) are to be used simultaneously, the values of sel_ssi7[0] and sel_ssi8[0] must be the same so
that the selected pins belong to the same group. If this is not the case, correct operation is not guaranteed.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
sel_adg
[1]
sel_adg
[0]
—
sel_can
[1]
sel_can
[0]
— — — — — — —
sel_eth
[0]
—
sel_i2c
00[2]
sel_i2c
00[1]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sel_i2c
00[0]
sel_i2c
01[2]
sel_i2c
01[1]
sel_i2c
01[0]
sel_i2c
02[2]
sel_i2c
02[1]
sel_i2c
02[0]
sel_i2c
03[2]
sel_i2c
03[1]
sel_i2c
03[0]
sel_i2c
04[2]
sel_i2c
04[1]
sel_i2c
04[0]
sel_i2c
05[1]
sel_i2c
05[0]
sel_avb
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W These bits select multiplexed pin functions as indicated in the table
below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value = H'0)
Function 2
(Set Value = H'1)
Function 3
(Set Value = H'2)
Function 4
(Set Value = H'3)
Function 5
(Set Value = H'4)
sel_adg[1:0] + select pin AUDIO_CLKA for
function AUDIO_CLKA + select
pin AUDIO_CLKB for function
AUDIO_CLKB + select pin
AUDIO_CLKC for function
AUDIO_CLKC + select pin
AUDIO_CLKOUT for function
AUDIO_CLKOUT + select pin HSCIF0_HRX for
function AUDIO_CLKA_B +
select pin HSCIF0_HSCK for
function AUDIO_CLKC_B +
select pin HSCIF0_HTX for
function AUDIO_CLKB_B +
select pin VI0_VSYNC_N for
function AUDIO_CLKOUT_B + select pin I2C2_SCL for
function AUDIO_CLKC_C +
select pin I2C2_SDA for
function AUDIO_CLKOUT_C +
select pin SCIF3_RXD for
function AUDIO_CLKA_C +
select pin SCIF3_TXD for
function AUDIO_CLKB_C + select pin SSI_SDATA7 for
function AUDIO_CLKA_D
sel_can[1:0] + select pin I2C0_SDA for
function CAN_CLK + select pin EX_WAIT0 for
function CAN_CLK_B + select pin A16 for function
CAN_CLK_C + select pin SSI_SDATA7 for
function CAN_CLK_D