Renesas RZ/G1E, User Manual

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RZ/G1E 5. Pin Function Controller (PFC)
R01UH0544EJ0100 Rev.1.00 5-63
Sep 30,2016
5.3.35 TDSEL Control Register (IOCTRL2)
Function: IOCTRL2 controls the delay of clock of pins in use for the IRQ, DU and Ethernet interfaces.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tdsel1_a
10
tdsel0_a
10
tdsel1_a
16
tdsel0_a
16
tdsel1_a
udioclkb
tdsel0_a
udioclkb
tdsel1_et
hrxer
tdsel0_et
hrxer
tdsel1_e
xcs3n
tdsel0_e
xcs3n
tdsel1_i2
c1sda
tdsel0_i2
c1sda
tdsel1_m
mcclk
tdsel0_m
mcclk
tdsel1_m
siof0sck
tdsel0_m
siof0sck
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tdsel1_m
siof0sync
tdsel0_m
siof0sync
tdsel1_s
d0clk
tdsel0_s
d0clk
tdsel1_s
d1clk
tdsel0_s
d1clk
tdsel1_s
sisdata0 tdsel0_s
sisdata0
— — — — — — — —
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W
Description
31 tdsel1_a10 0 R/W A10 Setting.
The value of these bits must be 00.
30 tdsel0_a10 0 R/W
29 tdsel1_a16 0 R/W A16 Setting.
The value of these bits must be 00.
28 tdsel0_a16 0 R/W
27 tdsel1_audioclkb 0 R/W AUDIO_CLKB Setting.
The value of these bits must be 00.
26 tdsel0_audioclkb 0 R/W
25 tdsel1_ethrxer 0 R/W ETH_RX_ER Setting.
The value of these bits must be 00.
24 tdsel0_ethrxer 0 R/W
23 tdsel1_excs3n 0 R/W EX_CS3_N Setting.
The value of these bits must be 00.
22 tdsel0_excs3n 0 R/W
21 tdsel1_i2c1sda 0 R/W I2C1_SDA Setting.
The value of these bits must be 00.
20 tdsel0_i2c1sda 0 R/W
19 tdsel1_mmcclk 0 R/W MMC_CLK Setting.
The value of these bits must be 00.
18 tdsel0_mmcclk 0 R/W
17 tdsel1_msiof0sck 0 R/W MSIOF0_SCK Setting.
The value of these bits must be 00.
16 tdsel0_msiof0sck 0 R/W
15 tdsel1_msiof0sync 0 R/W MSIOF0_SYNC Setting.
The value of these bits must be 00.
14 tdsel0_msiof0sync 0 R/W
13 tdsel1_sd0clk 0 R/W SD0_CLK Setting.
The value of these bits must be 00.
12 tdsel0_sd0clk 0 R/W
11 tdsel1_sd1clk 0 R/W SD1_CLK Setting.
The value of these bits must be 00.
10 tdsel0_sd1clk 0 R/W
9 tdsel1_ssisdata0 0 R/W SSI_SDATA0 Setting.
The value of these bits must be 00.
8 tdsel0_ssisdata0 0 R/W
7 to 0 — All 0 R/W —
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.