Renesas RZ/G1E, User Manual

Page: 27 / 141

RZ/G1E 1. Overview
R01UH0544EJ0100 Rev.1.00 1-20
Sep 30,2016
Item Description
Serial communication
interface with FIFO
(SCIF) Overall
specification 
6 channels

Asynchronous, clock-synchronized modes

Asynchronous serial communication mode
The SCIF performs serial data communication based on a character-by-
character asynchronous system. This feature enables serial data
communication with standard asynchronous communication chips that
support Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA). There is a
choice of eight serial data transfer formats.

Data length: 7 bits or 8 bits

Stop bits: 1 bit or 2 bits

Parity: Even/odd/none

Receive error detection: Parity, framing, and overrun errors

Break detection:
A break is detected when a framing error lasts for more than 1 frame
length at Space 0 (low level).
When a framing error occurs, a break can also be detected by reading
the RX pin level directly from the serial port register (SCSPTR).

Clock synchronous serial communication mode
The SCIF performs serial data communication synchronized with a clock.
This feature enables serial data communication with other LSIs that
support synchronous communication. There is a single serial data
communication format for clock synchronous serial communication.

Data length: 8 bits

Receive error detection: Overrun errors

Full-duplex communication capability
The SCIF has an independent transmitter and receiver that enable
simultaneous transmission and reception. The transmitter and receiver
both have a 16-stage FIFO buffer structure, enabling continuous serial
data transmission and reception.

On-chip baud rate generator, enabling any bit rate to be selected
The SCIF enables choice of a clock source for transmission/reception: a
clock from the on-chip baud rate generator based on the internal clock or
an external clock.

Eight interrupt sources
The SCIF has eight types of interrupt sources: receive-data-ready,
receive-FIFO-data-full, break, transmit-FIFO-data-empty, transmit-end,
receive-error, overrun-error and time-out and enables any of them to be
requested independently.

DMA data transfer
When the transmit FIFO register is empty or the receive FIFO register has
received data, issuing a DMA transfer request activates the DMA
controller (DMAC) to execute a data transfer.

The amount of data in the transmit/receive FIFO registers and the number
of receive errors in receive data in the receive FIFO register are available.

In asynchronous mode, a receive data ready (DR) or a timeout error (TO)
can be detected during reception.