Renesas H8S/2111B Hardware Manual Download Page 326 | Manualshive

Page: 326 / 582

background image

Rev. 1.00, 05/04, page 292 of 544

Bit Bit

Name

Initial
Value

R/W Description

1 IRIC

0 R/(W)

*

I

2

C Bus Interface Interrupt Request Flag

Indicates that the I

2

C bus interface has issued an

interrupt request to the CPU.

IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 13.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in ICCR.

[Setting conditions]

I

2

C bus format master mode:

•

When a start condition is detected in the bus line
state after a start condition is issued (when the
ICDRE flag is set to 1 because of first frame
transmission)

•

When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the
8th transmit/receive clock)

•

At the end of data transfer (rise of the 9th
transmit/receive clock while no wait is inserted)

•

When a slave address is received after bus
arbitration is lost (the first frame after the start
condition)

•

If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) when the ACKE bit is
1

•

When the AL flag is set to 1 after bus arbitration is
lost while the ALIE bit is 1

I

2

C bus format slave mode:

•

When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1)
and at the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th transmit/receive clock)

•

When the general call address is detected (when 0
is received as the R/

W

bit and the ADZ flag in ICSR

is set to 1) and at the end of data reception up to
the subsequent retransmission start condition or
stop condition detection (rise of the 9th receive
clock)

•

If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) while the ACKE bit is 1

•

When a stop condition is detected (when the STOP
or ESTP flag in ICSR is set to 1) while the STOPIM
bit is 0

«
...
324
325
326
327
328
...
»

Summary of Contents for H8S/2111B

Page 1: ...Revision Date May 14 2004 16 H8S 2111B Hardware Manual Renesas 16 Bit Single Chip Microcomputer H8S Family H8S 2100 Series H8S 2111B HD64F2111B Rev 1 00 REJ09B0163 0100Z...

Page 2: ...Rev 1 00 05 04 page ii of xxxiv...

Page 3: ...total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting fro...

Page 4: ...ization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on th...

Page 5: ...tems i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in...

Page 6: ...tions that will most probably change Note F ZTATTM is a trademark of Renesas Technology Corp Target Users This manual was written for users who will be using the H8S 2111B in the design of application...

Page 7: ...ated manuals are available from our web site Please ensure you have the latest versions of all documents you require http www renesas com eng H8S 2111B manuals Document Title Document No H8S 2111B Har...

Page 8: ...Rev 1 00 05 04 page viii of xxxiv...

Page 9: ...tended Control Register EXR 23 2 4 4 Condition Code Register CCR 24 2 4 5 Initial Register Values 25 2 5 Data Formats 26 2 5 1 General Register Data Formats 26 2 5 2 Memory Data Formats 28 2 6 Instruc...

Page 10: ...ources and Exception Vector Table 60 4 3 Reset 61 4 3 1 Reset Exception Handling 61 4 3 2 Interrupts after Reset 62 4 3 3 On Chip Peripheral Modules after Reset is Cancelled 62 4 4 Interrupt Exception...

Page 11: ...n 91 5 8 4 IRQ Status Register ISR 91 Section 6 Bus Controller BSC 93 6 1 Register Descriptions 93 6 1 1 Bus Control Register BCR 93 6 1 2 Wait State Control Register WSCR 94 Section 7 I O Ports 95 7...

Page 12: ...ort 8 Data Register P8DR 118 7 8 3 Pin Functions 119 7 9 Port 9 122 7 9 1 Port 9 Data Direction Register P9DDR 122 7 9 2 Port 9 Data Register P9DR 122 7 9 3 Pin Functions 123 7 10 Port A 125 7 10 1 Po...

Page 13: ...6 Pin Functions 145 Section 8 8 Bit PWM Timer PWM 147 8 1 Features 147 8 2 Input Output Pins 148 8 3 Register Descriptions 148 8 3 1 PWM Register Select PWSL 149 8 3 2 PWM Data Registers 7 to 0 PWDR7...

Page 14: ...r 177 9 7 2 Conflict between FRC Write and Increment 178 9 7 3 Conflict between OCR Write and Compare Match 178 9 7 4 Switching of Internal Clock and FRC Operation 180 9 7 5 Module Stop Mode Setting 1...

Page 15: ...es 216 10 10 1 Conflict between TCNT Write and Counter Clear 216 10 10 2 Conflict between TCNT Write and Count Up 216 10 10 3 Conflict between TCOR Write and Compare Match 217 10 10 4 Conflict between...

Page 16: ...d Reception Margin in Asynchronous Mode 251 12 4 3 Clock 251 12 4 4 SCI Initialization Asynchronous Mode 253 12 4 5 Data Transmission Asynchronous Mode 254 12 4 6 Serial Data Reception Asynchronous Mo...

Page 17: ...07 13 4 1 I2 C Bus Data Format 307 13 4 2 Initialization 309 13 4 3 Master Transmit Operation 309 13 4 4 Master Receive Operation 314 13 4 5 Slave Receive Operation 321 13 4 6 Slave Transmit Operation...

Page 18: ...7 Status Registers 1 to 3 STR1 to STR3 383 15 3 8 SERIRQ Control Registers 0 and 1 SIRQCR0 SIRQCR1 389 15 3 9 Host Interface Select Register HISEL 397 15 4 Operation 398 15 4 1 Host Interface Activati...

Page 19: ...tion 436 18 4 Input Output Pins 437 18 5 Register Descriptions 437 18 5 1 Flash Memory Control Register 1 FLMCR1 438 18 5 2 Flash Memory Control Register 2 FLMCR2 439 18 5 3 Erase Block Registers 1 an...

Page 20: ...ode 470 20 4 Sleep Mode 471 20 5 Software Standby Mode 471 20 6 Hardware Standby Mode 473 20 7 Watch Mode 474 20 8 Subsleep Mode 475 20 9 Subactive Mode 476 20 10 Module Stop Mode 477 20 11 Direct Tra...

Page 21: ...cs 527 22 6 Usage Note 529 22 7 Timing Chart 529 22 7 1 Clock Timing 529 22 7 2 Control Signal Timing 531 22 7 3 On Chip Peripheral Module Timing 532 Appendix 537 A I O Port States in Each Processing...

Page 22: ...Rev 1 00 05 04 page xxii of xxxiv...

Page 23: ...Figure 3 1 Address Map for H8S 2111B B 57 Figure 3 2 Address Map for H8S 2111B C 58 Section 4 Exception Handling Figure 4 1 Reset Sequence Mode 3 61 Figure 4 2 Stack Status after Exception Handling 64...

Page 24: ...e 9 13 Timing of Overflow Flag OVF Setting 175 Figure 9 14 OCRA Automatic Addition Timing 175 Figure 9 15 Timing of Input Capture Mask Signal Setting 176 Figure 9 16 Timing of Input Capture Mask Signa...

Page 25: ...Mode 252 Figure 12 5 Sample SCI Initialization Flowchart 253 Figure 12 6 Example of SCI Transmit Operation in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit 254 Figure 12 7 Sample Seria...

Page 26: ...peration Timing in Master Transmit Mode MLS WAIT 0 313 Figure 13 10 Sample Flowchart for Operations in Master Receive Mode HNDS 1 314 Figure 13 11 Example of Operation Timing in Master Receive Mode ML...

Page 27: ...wchart 355 Figure 14 4 Receive Timing 356 Figure 14 5 Sample Transmit Processing Flowchart 1 357 Figure 14 5 Sample Transmit Processing Flowchart 2 358 Figure 14 6 Transmit Timing 358 Figure 14 7 Samp...

Page 28: ...Programming Erasing Flowchart Example in User Program Mode 445 Figure 18 9 Program Program Verify Flowchart 447 Figure 18 10 Erase Erase Verify Flowchart 449 Figure 18 11 Memory Map in Programmer Mode...

Page 29: ...532 Figure 22 13 8 Bit Timer Output Timing 533 Figure 22 14 8 Bit Timer Clock Input Timing 533 Figure 22 15 8 Bit Timer Reset Input Timing 533 Figure 22 16 PWM PWMX Output Timing 533 Figure 22 17 SCK...

Page 30: ...Rev 1 00 05 04 page xxx of xxxiv...

Page 31: ...ble 2 12 Absolute Address Access Ranges 41 Table 2 13 Effective Address Calculation 1 44 Table 2 13 Effective Address Calculation 2 45 Section 3 MCU Operating Modes Table 3 1 MCU Operating Mode Select...

Page 32: ...to TCNT and Count Condition 1 193 Table 10 3 Clock Input to TCNT and Count Condition 2 194 Table 10 3 Clock Input to TCNT and Count Condition 3 195 Table 10 4 Registers Accessible by TMR_X TMR_Y 204 T...

Page 33: ...r tSf 339 Section 14 Keyboard Buffer Controller Table 14 1 Pin Configuration 350 Section 15 Host Interface LPC Table 15 1 Pin Configuration 371 Table 15 2 Register Selection 382 Table 15 3 GA20 P81 Se...

Page 34: ...22 1 Absolute Maximum Ratings 513 Table 22 2 DC Characteristics 1 514 Table 22 2 DC Characteristics 2 516 Table 22 2 DC Characteristics 3 When LPC Function is Used 517 Table 22 3 Permissible Output Cu...

Page 35: ...t timer TMR Watchdog timer WDT Asynchronous or clocked synchronous serial communication interface SCI I2 C bus interface IIC Keyboard buffer controller Host interface LPC 10 bit A D converter Clock pu...

Page 36: ...MD0 NMI STBY RESO VCC VCC VCL VSS VSS VSS VSS VSS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 P77 P76 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 P86 IRQ5 SCK1 SCL1 P85 IRQ4 R...

Page 37: ...N1 P60 FTCI KIN0 TMIX AVref AVCC P77 P76 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 AVSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PG0 PG1 PG2 PG3 PG4 ExSDAA PG5 ExSCLA PG6 ExSDAB PG7 ExSCLB PF0 TMIA PF1 T...

Page 38: ...ammer Mode 1 VCC VCC 2 P43 TMCI1 NC 3 P44 TMO1 NC 4 P45 TMRI1 NC 5 P46 NC 6 P47 NC 7 VSS VSS 8 RES RES 9 MD1 VSS 10 MD0 VSS 11 NMI FA9 12 STBY VCC 13 VCL VCC 14 N P52 ExSCK1 SCL0 FA18 15 P51 ExRxD1 FA...

Page 39: ...2BD NC 36 VCCB VCC 37 B PA4 KIN12 PS2BC NC 38 B PA3 KIN11 PS2AD NC 39 B PA2 KIN10 PS2AC NC 40 B PA1 KIN9 NC 41 B PA0 KIN8 NC 42 VSS VSS 43 PF7 TMOY NC 44 PF6 ExTMOX NC 45 PF5 ExTMIY NC 46 PF4 ExTMIX N...

Page 40: ...NC 67 AVSS VSS 68 P70 AN0 NC 69 P71 AN1 NC 70 P72 AN2 NC 71 P73 AN3 NC 72 P74 AN4 NC 73 P75 AN5 NC 74 P76 NC 75 P77 NC 76 AVCC VCC 77 AVref VCC 78 P60 FTCI KIN0 TMIX NC 79 P61 FTOA KIN1 NC 80 P62 FTI...

Page 41: ...96 P27 CE 97 P26 FA14 98 P25 FA13 99 P24 FA12 100 P23 FA11 101 P22 FA10 102 P21 OE 103 P20 FA8 104 P17 PW7 FA7 105 P16 PW6 FA6 106 P15 PW5 FA5 107 P14 PW4 FA4 108 P13 PW3 FA3 109 P12 PW2 FA2 110 P11 P...

Page 42: ...SERIRQ FO7 129 P80 PME NC 130 P81 GA20 NC 131 P82 CLKRUN NC 132 P83 LPCPD NC 133 P84 IRQ3 TxD1 NC 134 P85 IRQ4 RxD1 NC 135 N P86 IRQ5 SCK1 SCL1 NC 136 P40 TMCI0 NC 137 P41 TMO0 NC 138 N P42 TMRI0 SDA...

Page 43: ...ock Pulse Generator for typical connection diagrams 18 Output Supplies the system clock to external devices EXCL 18 Input Input a 32 768 kHz external subclock X1 140 Input Leave open Clock X2 141 Inpu...

Page 44: ...input to counters 8 bit timer TMR_0 TMR_1 TMR_X TMR_Y TMR_A TMR_B TMRI0 TMRI1 138 4 Input The counter reset input pins 8 bit timer TMR_X TMR_Y TMR_A TMR_B TMIX TMIY TMIA TMIB ExTMIX ExTMIY 78 80 50 4...

Page 45: ...D 132 Input Input pin that controls LPC module shutdown KIN0 to KIN15 78 to 85 41 to 37 35 to 33 Input Matrix keyboard input pins KIN0 to KIN15 are used as key scan inputs and P10 to P17 and P20 to P2...

Page 46: ...pins The output type of P52 is NMOS push pull P67 to P60 85 to 78 Input Output Eight input output pins P77 to P70 75 to 68 Input Eight input pins P86 to P80 135 to 129 Input Output Seven input output...

Page 47: ...s or eight 32 bit registers Sixty five basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes R...

Page 48: ...ter configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU The number of execut...

Page 49: ...nhanced Signed multiply and divide instructions have been added Two bit shift and two bit rotate instructions have been added Instructions for saving and restoring multiple registers have been added A...

Page 50: ...ons and addressing modes can be used Only the lower 16 bits of effective addresses EA are valid Exception vector table and memory indirect branch addresses In normal mode the top area starting at H 00...

Page 51: ...exception vector Reserved for system use Exception vector 1 Exception vector 2 Exception vector table Reserved for system use Figure 2 1 Exception Vector Table Normal Mode a Subroutine Branch b Excep...

Page 52: ...ory indirect branch addresses In advanced mode the top area starting at H 00000000 is allocated to the exception vector table in 32 bit units In each 32 bits the upper 8 bits are ignored and a branch...

Page 53: ...dresses can be stored in the area from H 00000000 to H 000000FF Note that the top area of this range is also used for the exception vector table Stack structure In advanced mode when the program count...

Page 54: ...ode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product refer to section 3 MCU...

Page 55: ...1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extended control register Trace bit Interrupt mask bits...

Page 56: ...re functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers When the general registers are used as 8 bit registers the R...

Page 57: ...e least significant PC bit is ignored When an instruction is fetched for read the least significant PC bit is regarded as 0 2 4 3 Extended Control Register EXR EXR does not affect operation in this LS...

Page 58: ...software using the LDC STC ANDC ORC and XORC instructions 5 H Undefined R W Half Carry Flag When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is...

Page 59: ...t accumulator by bit manipulation instructions 2 4 5 Initial Register Values The program counter PC among CPU internal registers is initialized when reset exception handling loads a start address from...

Page 60: ...treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats of general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care Don t care Don t...

Page 61: ...n RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Image Register Number Word...

Page 62: ...curs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches When SP ER7 is used as an address register to...

Page 63: ...ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch BCC 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC...

Page 64: ...register EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in...

Page 65: ...ck POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP PUSH L ERn is identical to...

Page 66: ...value 1 can be added to or subtracted from byte operands ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd D...

Page 67: ...0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of...

Page 68: ...es the one s complement logical complement of data in a general register Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function SHAL SHAR...

Page 69: ...operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C Logically ANDs the carry fl...

Page 70: ...er is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a spec...

Page 71: ...C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE G...

Page 72: ...mory The upper 8 bits are valid ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR or EXR contents with immed...

Page 73: ...ve two operation fields Register field Specifies a general register Address registers are specified by 3 bits and data registers by 3 bits or 4 bits Some instructions have two register fields and some...

Page 74: ...Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 16 ERn d 32 ERn 4 Register indirect with post increment Register indirect with pre decrement ERn ERn 5...

Page 75: ...ddress of a memory operand The result is also stored in the address register The value subtracted is 1 for byte access 2 for word access and 4 for longword access For word or longword transfer instruc...

Page 76: ...ctor address 2 7 7 Program Counter Relative d 8 PC or d 16 PC This mode can be used by the Bcc and BSR instructions An 8 bit or 16 bit displacement contained in the instruction code is sign extended t...

Page 77: ...ngword operand the first byte of which is assumed to be 0 H 00 Note that the top area of the address range in which the branch address is stored is also used for the exception vector area For further...

Page 78: ...p rm op rn 31 0 31 0 r op Don t care 31 23 31 0 Don t care 31 0 disp 31 0 31 0 31 23 31 0 Don t care 31 23 31 0 Don t care 24 24 24 24 Addressing Mode and Instruction Format Effective Address Calculat...

Page 79: ...24 24 Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d...

Page 80: ...xception Handling The reset state can also be entered by a watchdog timer overflow Exception handling state The exception handling state is a transient state that occurs when the CPU alters the normal...

Page 81: ...s low A transition can also be made to the reset state when the watchdog timer overflows From any state a transition to hardware standby mode occurs when STBY goes low The power down state also includ...

Page 82: ...fied in the register list Two registers ER0 ER1 ER2 ER3 or ER4 ER5 Three registers ER0 ER2 or ER4 ER6 Four registers ER0 ER3 The STM LDM instruction including ER7 is not generated by the Renesas Techn...

Page 83: ...ta indicated by R4L which starts from the address indicated by R5 to the address indicated by R6 R6 R6 R4L R5 R5 R4L 2 Set R4L and R6 so that the end address of the destination address value of R6 R4L...

Page 84: ...Rev 1 00 05 04 page 50 of 544...

Page 85: ...selection Table 3 1 lists the MCU operating modes Table 3 1 MCU Operating Mode Selection MCU Operating Mode MD1 MD0 CPU Operating Mode Description On Chip ROM 2 0 Advanced Single chip mode 3 1 1 Norm...

Page 86: ...ial value should not be changed 6 to 2 All 0 R Reserved These bits are always read as 0 These bits cannot be modified 1 0 MDS1 MDS0 R R Mode Select 1 and 0 These bits indicate the input levels at mode...

Page 87: ...interrupt controller For details on the interrupt control modes and interrupt control select modes 1 and 0 see section 5 6 Interrupt Control Modes and Interrupt Operation 00 Interrupt control mode 0...

Page 88: ...TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X and TCORB_X TCONRI and TCONRS 0 In areas H FF FFF0 to H FF FFF7 and H FF FFFC to H FF FFFF CPU access to 8 bit timer TMR_X and TMR_Y is permitted 1 In areas H...

Page 89: ...iving 6 5 IICX1 IICX0 0 0 R W R W I 2 C Transfer Rate Select 1 and 0 These bits control the IIC operation These bits select a transfer rate in master mode together with bits CKS2 to CKS0 in the I 2 C...

Page 90: ...memory are accessed in an area from H FF FF80 to H FF FF87 2 0 R W Reserved The initial value should not be changed 1 0 ICKS1 ICKS0 0 0 R W R W Internal Clock Source Select 1 0 These bits select a clo...

Page 91: ...ters 3 Reserved area Reserved area H 01FFFF H 000000 H FFE080 H FFE880 H FFFEFF H FFFFFF H FFFE50 H FFFF7F H FFFF80 H FFFF00 H FFF800 H FFFE4F H FFEFFF H 00FFFF Mode 3 EXPE 0 Normal mode Single chip m...

Page 92: ...FFF H 000000 H FFE080 H FFE480 H FFFEFF H FFFFFF H FFFE50 H FFFF7F H FFFF80 H FFFF00 H FFF800 H FFFE4F H FFEFFF H 00FFFF Mode 3 EXPE 0 Normal mode Single chip mode H DFFF H 0000 On chip ROM Internal I...

Page 93: ...ling Reset Starts immediately after a low to high transition of the RES pin or when the watchdog timer overflows Interrupt Starts when execution of the current instruction or exception handling ends i...

Page 94: ...o H 0013 H 000024 to H 000027 10 H 0014 to H 0015 H 000028 to H 00002B Trap instruction four sources 11 H 0016 to H 0017 H 00002C to H 00002F Reserved for system use 12 15 H 0018 to H 0019 H 001E to H...

Page 95: ...r being held low for the necessary time this LSI starts reset exception handling as follows 1 The internal state of the CPU and the registers of the on chip peripheral modules are initialized and the...

Page 96: ...the first instruction of a program is always executed immediately after the reset state ends make sure that this instruction initializes the stack pointer example MOV L xx 32 SP 4 3 3 On Chip Peripher...

Page 97: ...p Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed Trap instruction exception handling can be executed at all times in the program executi...

Page 98: ...Handling Figure 4 2 shows the stack after completion of trap instruction exception handling and interrupt exception handling CCR CCR PC 16 bits Note Ignored on return Normal mode Advanced mode CCR PC...

Page 99: ...registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 3 shows an example of what happens when the SP value is odd SP CCR PC R1L SP...

Page 100: ...Rev 1 00 05 04 page 66 of 544...

Page 101: ...ndent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Thirty one external interrupts NMI is the highest priority interrupt and is accepted at a...

Page 102: ...gister Legend KIN and WUE input KMIMR WUEMR KIN input WUE input Figure 5 1 Block Diagram of Interrupt Controller 5 2 Input Output Pins Table 5 1 summarizes the pins of the interrupt controller Table 5...

Page 103: ...register ISR Keyboard matrix interrupt mask registers KMIMRA KMIMR Wake up event interrupt mask register WUEMRB 5 3 1 Interrupt Control Registers A to C ICRA to ICRC The ICR registers set interrupt c...

Page 104: ...CR controls the address breaks When both the CMF flag and BIE flag are set to 1 an address break is requested Bit Bit Name Initial Value R W Description 7 CMF 0 R Condition Match Flag Address break so...

Page 105: ...cription 7 to 0 A23 to A16 All 0 R W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus BARB Bit Bit Name Initial Value R W Description 7 to 0 A15 to A8 Al...

Page 106: ...nerated at falling edge of IRQn input 10 Interrupt request generated at rising edge of IRQn input 11 Interrupt request generated at both falling and rising edges of IRQn input n 7 to 4 ISCRL Bit Bit N...

Page 107: ...Q5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Setting condition When the interrupt source selected by the ISCR registers occurs Clearing conditions When reading IRQ...

Page 108: ...KMIMR1 KMIMR0 1 0 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Keyboard Matrix Interrupt Mask 7 to 0 These bits enable or disable a key sensing input interrupt request KIN7 to KIN0 KMIMR6 also performs...

Page 109: ...al IRQ7E IRQ7SC IRQ7 interrupt KMIMR8 initial value 1 PA0 KIN8 KMIMR9 initial value 1 PA1 KIN9 WUEMR7 initial value 1 PB7 WUE7 Figure 5 2 Relationship between Interrupts IRQ7 and IRQ6 Interrupts KIN15...

Page 110: ...for interrupt requests IRQ7 to IRQ0 can be started at an independent vector address Using ISCR it is possible to select whether an interrupt is generated by a low level falling edge rising edge or bo...

Page 111: ...0 and KIN15 to KIN8 generate IRQ7 interrupts and interrupts KIN7 to KIN0 generate IRQ6 interrupts The pin conditions for interrupt request generation enable of interrupt requests settings of interrupt...

Page 112: ...ctor Number Normal Mode Advanced Mode ICR Priority NMI 7 H 000E H 00001C High IRQ0 16 H 0020 H 000040 ICRA7 IRQ1 17 H 0022 H 000044 ICRA6 IRQ2 IRQ3 18 19 H 0024 H 0026 H 000048 H 00004C ICRA5 IRQ4 IRQ...

Page 113: ...00AA H 00AC H 00AE H 000150 H 000154 H 000158 H 00015C ICRC6 Reserved for system use 88 to 91 H 00B0 to H 00B6 H 000160 to H 00016C IIC_0 IICI0 1 byte transmission reception completion Reserved for s...

Page 114: ...the corresponding interrupt enable bit is set to 1 an interrupt request is sent to the interrupt controller 2 According to the interrupt control level specified in ICR the interrupt controller only a...

Page 115: ...or address in the vector table Program excution state Interrupt generated NMI An interrupt with interrupt control level 1 IRQ0 IRQ1 IBFI3 IRQ0 IRQ1 IBFI3 I 0 Save PC and CCR I 1 Read vector address Br...

Page 116: ...pt enable bit corresponding to each interrupt is set to 1 and ICRA to ICRC are set to H 20 H 00 and H 00 respectively IRQ2 and IRQ3 interrupts are set to control level 1 and other interrupts are set t...

Page 117: ...upt request with interrupt control level 0 is accepted when the I bit is cleared to 0 When the I bit is set to 1 only an NMI or address break interrupt request is accepted and other interrupts are hel...

Page 118: ...vel 1 IRQ0 IRQ1 IFBFI3 IRQ0 IRQ1 IFBFI3 UI 0 Save PC and CCR I 1 UI 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Yes No No Yes Yes No Hold pend...

Page 119: ...epted Interrupt level decision and wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus 3 1 2 4 3 5 7 Instruction pref...

Page 120: ...es until executing instruction ends 2 1 to 19 2 SI 3 PC CCR stack save 2 SK 2 SK 4 Vector fetch SI 2 SI 5 Instruction fetch 3 2 SI 6 Internal processing 4 2 Total using on chip memory 11 to 31 12 to 3...

Page 121: ...address break interrupt exception handling is performed With this function the execution start point of a program containing a bug is detected and execution is branched to the correcting program 5 7...

Page 122: ...to 1 to request an interrupt The interrupt source should be determined by the interrupt handling routine if necessary 5 7 4 Usage Notes 1 In an address break the break address should be an address whe...

Page 123: ...eak address specified instruction is executed for one state in the program area and on chip memory Address bus Break request signal Break point MOV instruction is executed at break point address H 031...

Page 124: ...cuted on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the higher priority interrupt a...

Page 125: ...instruction and the EEPMOV W instruction With the EEPMOV B instruction an interrupt request including NMI issued during the transfer is not accepted until the move is completed With the EEPMOV W inst...

Page 126: ...Rev 1 00 05 04 page 92 of 544...

Page 127: ...ister BCR Wait state control register WSCR 6 1 1 Bus Control Register BCR Bit Bit Name Initial Value R W Description 7 1 R W Reserved The initial value should not be changed 6 ICIS0 1 R W Idle Cycle I...

Page 128: ...itial value should not be changed 5 ABW 1 R W Bus Width Control The initial value should not be changed 4 AST 1 R W Access State Control The initial value should not be changed 3 2 WMS1 WMS0 0 0 R W R...

Page 129: ...R to control the on off state of the input pull up MOS Ports 1 to 6 8 9 and A to F can drive a single TTL load and 30 pF capacitive load All the I O ports can drive a Darlington transistor when in out...

Page 130: ...P20 On chip input pull up MOSs Port 3 General I O port also functioning as LPC input output pins P37 SERIRQ P36 LCLK P35 LRESET P34 LFRAME P33 LAD3 P32 LAD2 P31 LAD1 P30 LAD0 On chip input pull up MOS...

Page 131: ...ll up MOSs Port 7 General input port also functioning as A D converter analog input P77 P76 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 Port 8 General I O port also functioning as interrupt input...

Page 132: ...2BC PA3 KIN11 PS2AD PA2 KIN10 PS2AC PA1 KIN9 PA0 KIN8 On chip input pull up MOSs Port B General I O port also functioning as wakeup event interrupt input and LPC input output pins PB7 WUE7 PB6 WUE6 PB...

Page 133: ...also functioning as TMR_X TMR_Y TMR_A and TMR_B input output pins PF7 TMOY PF6 ExTMOX PF5 ExTMIY PF4 ExTMIX PF3 TMOB PF2 TMOA PF1 TMIB PF0 TMIA On chip input pull up MOSs Port G General I O port also...

Page 134: ...P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W The corresponding port 1 pins are output ports when the P1DDR bits are set to 1 and input ports when the P1DDR...

Page 135: ...14PCR 0 R W 3 P13PCR 0 R W 2 P12PCR 0 R W 1 P11PCR 0 R W 0 P10PCR 0 R W When a P1PCR bit is set to 1 with the input port setting the input pull up MOS is turned on 7 1 4 Pin Functions P17 PW7 to P10 P...

Page 136: ...state P1DDR 0 and P1PCR 1 otherwise off 7 2 Port 2 Port 2 is an 8 bit I O port Port 2 has an on chip input pull up MOS function that can be controlled by software Port 2 has the following registers Po...

Page 137: ...DR bits are cleared to 0 the pin states are read 7 2 3 Port 2 Pull Up MOS Control Register P2PCR P2PCR controls the port 2 on chip input pull up MOSs Bit Bit Name Initial Value R W Description 7 P27PC...

Page 138: ...is in the input state P2DDR 0 and P2PCR 1 otherwise off 7 3 Port 3 Port 3 is an 8 bit I O port Port 3 pins also function as LPC input output pins Port 3 has the following registers Port 3 data direct...

Page 139: ...e actual pin states If a port 3 read is performed while P3DDR bits are cleared to 0 the pin states are read 7 3 3 Port 3 Pull Up MOS Control Register P3PCR P3PCR controls the port 3 on chip input pull...

Page 140: ...table must not be used m 3 to 1 LPC input output pins SERIRQ LCLK LRESET LFRAME LAD3 to LAD0 when at least one of LPC3E to LPC1E is set to 1 n 7 to 0 7 3 5 Port 3 Input Pull Up MOS Port 3 has an on ch...

Page 141: ...lue R W Description 7 P47DDR 0 W 6 P46DDR 0 W 5 P45DDR 0 W 4 P44DDR 0 W 3 P43DDR 0 W 2 P42DDR 0 W 1 P41DDR 0 W 0 P40DDR 0 W When a bit in P4DDR is set to 1 the corresponding pin functions as an output...

Page 142: ...pin P46 output pin P45 TMRI1 The pin function is switched as shown below according to the combination of the P45DDR bit P45DDR 0 1 P45 input pin P45 output pin Pin Function TMRI1 input pin Note When...

Page 143: ...only output and has direct bus drive capability When bits CCLR1 and CCLR0 in TCR0 of TMR_0 are set to 1 this pin is used as the TMRI0 input pin When the P42 output pin is set the output type is NMOS p...

Page 144: ...be changed 2 P52DDR 0 W 1 P51DDR 0 W 0 P50DDR 0 W The corresponding port 5 pins are output ports when P5DDR bits are set to 1 and input ports when cleared to 0 As SCI_1 is initialized in software stan...

Page 145: ...0 I O pin Note 1 When this pin is used as the SCL0 I O pin by setting 1 to the SPS1 bit of SPSR the bits CKE1 and CKE0 in SCR of SCI_1 and the C A bit in SMR must all be cleared to 0 SCL0 is an NMOS o...

Page 146: ...FRT I O pins TMR_X I O pins TMR_Y input pin key sense interrupt input pins and interrupt input pins Port 6 has the following registers Port 6 data direction register P6DDR Port 6 data register P6DR P...

Page 147: ...lues are read directly regardless of the actual pin states If a port 6 read is performed while P6DDR bits are cleared to 0 the pin states are read 7 6 3 Port 6 Pull Up MOS Control Register KMPCR KMPCR...

Page 148: ...pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X the IOSX bit 2 in TCRXY and the P67DDR bit IOSX 2 0 1 OS3 to OS0 All 0 Not all 0 P67DDR 0 1...

Page 149: ...ote This pin can always be used as the FTID or KIN5 input pin P64 FTIC KIN4 The pin function is switched as shown below according to the state of the P64DDR bit P64DDR 0 1 P64 input pin P64 output pin...

Page 150: ...e FRT It can always be used as the KIN0 input pin When the IOSX bit in TCRXY of TMR_X is set to 0 this pin can be used as the TMIX input pin 7 6 6 Port 6 Input Pull Up MOS Port 6 has an on chip input...

Page 151: ...R 4 P74PIN Undefined R 3 P73PIN Undefined R 2 P72PIN Undefined R 1 P71PIN Undefined R 0 P70PIN Undefined R When a P7PIN read is performed the pin states are always read P7PIN has the same address as...

Page 152: ...should not be changed 6 P86DDR 0 W 5 P85DDR 0 W 4 P84DDR 0 W 3 P83DDR 0 W 2 P82DDR 0 W 1 P81DDR 0 W 0 P80DDR 0 W P8DDR has the same address as PBPIN and if read the port B state will be returned The c...

Page 153: ...e SCL1 I O pin bits CKE1 and CKE0 in SCR of SCI_1 and bit C A in SMR of SCI_1 must all be cleared to 0 When the P86 output pin and SCK1 output pin are set the output type is NMOS push pull output SCL1...

Page 154: ...ator does not support this function P83 LPCPD The pin function is switched as shown below according to the state of the P83DDR bit P83DDR 0 1 P83 input pin P83 output pin Pin Function LPCPD input pin...

Page 155: ...output pin Pin Function GA20 input pin Note When bit FGA20E is set to 1 in HICR0 the P81DDR bit should be cleared to 0 P80 PME The pin function is switched as shown below according to the combination...

Page 156: ...1 P91DDR 0 W 0 P90DDR 0 W When the corresponding P9DDR bits are set to 1 pin P96 functions as the output pin and pins P97 and P95 to P90 become output ports When P9DDR bits are cleared to 0 the corres...

Page 157: ...PGCTL Thus P97ICE is treated as ICE P96 EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit P96DDR 0 1 EXCLE 0 1 0 Pin Function...

Page 158: ...e of the P91DDR bit P91DDR 0 1 P91 input pin P91 output pin Pin Function IRQ1 input pin Note When bit IRQ1E in IER is set to 1 this pin is used as the IRQ1 input pin P90 IRQ2 ADTRG The pin function is...

Page 159: ...Bit Bit Name Initial Value R W Description 7 PA7DDR 0 W 6 PA6DDR 0 W 5 PA5DDR 0 W 4 PA4DDR 0 W 3 PA3DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0 W 0 PA0DDR 0 W The corresponding port A pins are output ports when P...

Page 160: ..._2 of the keyboard buffer controller and the PA7DDR bit KBIOE 0 1 PA7DDR 0 1 PA7 input pin PA7 output pin PS2CD output pin Pin Function KIN15 input pin PS2CD input pin Note When the KBIOE bit is set t...

Page 161: ...BCRH_1 of the keyboard buffer controller and the PA4DDR bit KBIOE 0 1 PA4DDR 0 1 PA4 input pin PA4 output pin PS2BC output pin Pin Function KIN12 input pin PS2BC input pin Note When the KBIOE bit is s...

Page 162: ...An output pin Pin Function KINm input pin Note This pin can always be used as the KINm input pin n 1 or 0 m 9 or 8 7 10 5 Port A Input Pull Up MOS Port A has an on chip input pull up MOS function that...

Page 163: ...e R W Description 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W PBDDR has the same address as P7PIN and if read the port 7 pin states will be...

Page 164: ...he PB7 to PB0 pin states 7 11 4 Pin Functions PB7 WUE7 PB6 WUE6 PB5 WUE5 PB4 WUE4 PB3 WUE3 PB2 WUE2 The pin function is switched as shown below according to the state of the PBnDDR bit PBnDDR 0 1 PBn...

Page 165: ...E0 or LSMI input pin 7 11 5 Port B Input Pull Up MOS Port B has an on chip input pull up MOS function that can be controlled by software This input pull up MOS function can be specified as on or off o...

Page 166: ...DDR PCDDR and PDDDR select input or output for the pins of port C and port D on a bit by bit basis Bit Bit Name Initial Value R W Description 7 PC7DDR 0 W 6 PC6DDR 0 W 5 PC5DDR 0 W 4 PC4DDR 0 W 3 PC3D...

Page 167: ...W 4 PD4ODR 0 R W 3 PD3ODR 0 R W 2 PD2ODR 0 R W 1 PD1ODR 0 R W 0 PD0ODR 0 R W PDODR can always be read or written to regardless of the contents of PDDDR 7 12 3 Port C and Port D Input Data Registers P...

Page 168: ...ch OD Control Register PCNOCR PDNOCR PCNOCR and PDNOCR specify the output driver type for pins on ports C and D which are configured as outputs on a bit by bit basis Bit Bit Name Initial Value R W Des...

Page 169: ...ave an on chip input pull up MOS function that can be controlled by software This input pull up MOS function can be switched on or off on a bit by bit basis Table 7 8 is a summary of the input pull up...

Page 170: ...unction 7 13 1 Port E and Port F Data Direction Registers PEDDR PFDDR PEDDR and PFDDR select input or output for the pins of port E and port F on a bit by bit basis Bit Bit Name Initial Value R W Desc...

Page 171: ...E6ODR 0 R W 5 PE5ODR 0 R W 4 PE4ODR 0 R W 3 PE3ODR 0 R W 2 PE2ODR 0 R W 1 PE1ODR 0 R W 0 PE0ODR 0 R W PEODR can always be read or written to regardless of the contents of PEDDR Bit Bit Name Initial Va...

Page 172: ...W Description 7 PF7PIN Undefined R 6 PF6PIN Undefined R 5 PF5PIN Undefined R 4 PF4PIN Undefined R 3 PF3PIN Undefined R 2 PF2PIN Undefined R 1 PF1PIN Undefined R 0 PF0PIN Undefined R PFPIN indicates t...

Page 173: ...put pin Pin Function ExTMIY input pin Note The program development tool emulator does not support this function When the IOSY bit is set to 1 this pin can be used as the ExTMIY input pin PF4 ExTMIX Th...

Page 174: ...IB input pin PF0 TMIA The pin function is switched as shown below according to the state of the PF0DDR bit PF0DDR 0 1 PF0 input pin PF0 output pin Pin Function TMIA input pin Note This pin can always...

Page 175: ...nction Input pin Output pin Note Includes when set as the timer output pin 7 13 7 Input Pull Up MOS in Ports E and F Port E and port F have an on chip input pull up MOS function that can be controlled...

Page 176: ...PGDDR Port G output data register PGODR Port G input data register PGPIN Port G Nch OD control register PGNOCR Port G control register PGCTL Note The program development tool emulator does not suppor...

Page 177: ...dless of the contents of PGDDR 7 14 3 Port G Input Data Register PGPIN Reading PGPIN always returns the pin states Bit Bit Name Initial Value R W Description 7 PG7PIN Undefined R 6 PG6PIN Undefined R...

Page 178: ...es not support this function The output type of ExSDAB is NMOS open drain output and this pin has direct bus drive capability PG5 ExSCLA The pin function is switched as shown below according to the co...

Page 179: ...ed as outputs on a bit by bit basis Bit Bit Name Initial Value R W Description 7 PG7NOCR 0 R W 6 PG6NOCR 0 R W 5 PG5NOCR 0 R W 4 PG4NOCR 0 R W 3 PG3NOCR 0 R W 2 PG2NOCR 0 R W 1 PG1NOCR 0 R W 0 PG0NOCR...

Page 180: ...Rev 1 00 05 04 page 146 of 544...

Page 181: ...nverted PWM output and PWM output enable disable control Figure 8 1 shows a block diagram of the PWM timer P10 PW0 P11 PW1 P12 PW2 P13 PW3 P14 PW4 P15 PW5 P16 PW6 P17 PW7 Comparator 0 Comparator 1 Com...

Page 182: ...r Descriptions The PWM has the following registers To access PCSR the FLSHE bit in the serial timer control register STCR must be cleared to 0 For details on the serial timer control register STCR see...

Page 183: ...e following equations Resolution minimum pulse width 1 internal clock frequency PWM conversion period resolution 256 Carrier frequency 16 PWM conversion period With a 10 MHz system clock the resolutio...

Page 184: ...096 is selected Note The program development tool emulator does not support this function Table 8 3 Resolution PWM Conversion Period and Carrier Frequency when 10 MHz Internal Clock Frequency Resoluti...

Page 185: ...ulses are to be added within the conversion period comprising 16 basic pulses Thus a specification of 0 256 to 255 256 is possible for 0 1 ratios within the conversion period For 256 256 100 output po...

Page 186: ...when DDR 1 and OE 0 the corresponding pin should be set to port output DR data is output when the corresponding pin is used as port output A value corresponding to PWM 256 256 output is determined by...

Page 187: ...lution of 1 16 Table 8 4 shows the duty cycles of the basic pulse Table 8 4 Duty Cycle of Basic Pulse 0 H L 1 2 3 4 5 6 7 8 9 A B C D E F 0 Upper 4 Bits Basic Pulse Waveform Internal B 0 0 0 0 B 0 0 0...

Page 188: ...Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B 0000 B 0001 Yes B 0010 Yes Yes B 0011 Yes Yes Yes B 0100 Yes Yes Yes Yes B 0101 Yes Yes Yes Yes Yes B 0110 Yes Yes Yes Yes Yes Yes B 0111 Yes Yes Yes Yes...

Page 189: ...256 130 256 PWDR setting example H 7F H 80 H 81 H 82 112 pulses 128 pulses 128 pulses 128 pulses 15 pulses 0 pulses 1 pulse 2 pulses Figure 8 3 Example of PWM Setting 8 4 2 Diagram of PWM Used as D A...

Page 190: ...e Stop Mode Setting PWM operation can be enabled or disabled by the module stop control register In the initial state PWM operation is disabled Access to PWM registers is enabled when module stop mode...

Page 191: ...endent waveforms can be output Four independent input capture channels The rising or falling edge can be selected Buffer modes can be specified Counter clearing The free running counters can be cleare...

Page 192: ...signal Legend OCRA OCRB OCRAR OCRAF OCRDM FRC ICRA to ICRD TCSR TIER TCR TOCR Output compare register A B 16 bit Output compare register AR AF 16 bit Output compare register DM 16 bit Free running cou...

Page 193: ...Input capture D input 9 3 Register Descriptions The FRT has the following registers Free running counter FRC Output compare register A OCRA Output compare register B OCRB Input capture register A ICRA...

Page 194: ...it units OCR is initialized to H FFFF 9 3 3 Input Capture Registers A to D ICRA to ICRD The FRT has four input capture registers ICRA to ICRD each of which is a 16 bit read only register When the risi...

Page 195: ...ternal clock 2 as the FRC input clock together with a set value of H 0001 or less for OCRAR or OCRAF OCRAR and OCRAF should always be accessed in 16 bit units cannot be accessed in 8 bit units OCRAR a...

Page 196: ...ested by ICFB is disabled 1 ICIB requested by ICFB is enabled 5 ICICE 0 R W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request ICIC when input capture flag C...

Page 197: ...ested by OVF is enabled 0 0 R Reserved This bit is always read as 1 and cannot be modified 9 3 7 Timer Control Status Register TCSR TCSR is used for counter clear selection and control of interrupt re...

Page 198: ...e signal specified by the IEDGC bit at the FTIC input pin ICFC is set but data is not transferred to ICRC In buffer operation ICFC can be used as an external interrupt signal by setting the ICICE bit...

Page 199: ...be written to this bit to clear the flag Setting condition When FRC OCRB Clearing condition Read OCFB when OCFB 1 then write 0 to OCFB 1 OVF 0 R W Timer Overflow This status flag indicates that the F...

Page 200: ...apture on the rising edge of FTIB 5 IEDGC 0 R W Input Edge Select C Selects the rising or falling edge of the input capture C signal FTIC 0 Capture on the falling edge of FTIC 1 Capture on the rising...

Page 201: ...Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM 0 The normal operating mode is specified for ICRD 1 The operating mode using OCRDM is specified...

Page 202: ...Enable B Enables or disables output of the output compare B output pin FTOB 0 Output compare B output is disabled 1 Output compare B output is enabled 1 OLVLA 0 R W Output Level A Selects the level to...

Page 203: ...ws an example of 50 duty pulses output with an arbitrary phase difference When a compare match occurs while the CCLRA bit in TCSR is set to 1 the OLVLA and OLVLB bits are inverted by software H FFFF O...

Page 204: ...ternal clock source The pulse width of the external clock signal must be at least 1 5 system clocks The counter will not increment correctly if the pulse width is shorter than 1 5 system clocks Intern...

Page 205: ...he output compare pin FTOA or FTOB Figure 9 5 shows the timing of this operation for compare match A FRC OCRA N N N 1 N 1 N N Compare match A signal OLVLA Output compare A output pin FTOA Clear Note I...

Page 206: ...s selected Input capture input pin Input capture signal Figure 9 7 Input Capture Input Signal Timing Usual Case If ICRA to ICRAD are read when the corresponding input capture signal arrives the intern...

Page 207: ...uffer register its input capture flag is set by the selected transition of its input capture signal For example if ICRC is used to buffer ICRA when the edge transition selected by the IEDGC bit occurs...

Page 208: ...CFB ICFC or ICFD Setting 9 5 7 Timing of Output Compare Flag OCF setting The output compare flag OCFA or OCFB is set to 1 by a compare match signal generated when the FRC value matches the OCRA or OCR...

Page 209: ...al FRC H FFFF H 0000 OVF Figure 9 13 Timing of Overflow Flag OVF Setting 9 5 9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1 the contents of OCRAR and OCRAF are automatically added...

Page 210: ...ignal The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents and an FRC compare match Figure 9 15 shows the timing of setting the mask signal Figure 9 16 shows the tim...

Page 211: ...A Input capture of ICRA ICFA High ICIB Input capture of ICRB ICFB ICIC Input capture of ICRC ICFC ICID Input capture of ICRD ICFD OCIA Compare match of OCRA OCFA OCIB Compare match of OCRB OCFB FOVI O...

Page 212: ...7 3 Conflict between OCR Write and Compare Match If a compare match occurs during the state after an OCRA or OCRB write cycle the write takes priority and the compare match signal is disabled Figure...

Page 213: ...OCR Write and Compare Match When Automatic Addition Function is Not Used Address OCRAR OCRAF address Internal write signal Compare match signal FRC Automatic addition is not performed because compare...

Page 214: ...s changed when the old source is high and the new source is low as in case no 3 in table 9 3 the changeover is regarded as a falling edge that triggers the FRC clock and FRC is incremented Switching b...

Page 215: ...ck before switchover Clock after switchover FRC clock FRC N N 1 CKS bit rewrite N 2 Note Generated on the assumption that the switchover is a falling edge FRC is incremented 9 7 5 Module Stop Mode Set...

Page 216: ...Rev 1 00 05 04 page 182 of 544...

Page 217: ...mer output signal in each channel is controlled by two independent compare match signals enabling the timer to be used for various applications such as the generation of pulse output or PWM output wit...

Page 218: ...matchA Compare matchB External reset Compare matchA Compare matchB External reset Compare matchA Compare matchB External reset Pulse output O O O O O O Compare match output 0 output O O O O O O 1 out...

Page 219: ...w 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMRI1 Clock select Control logic Clear 0 TMR_1 2 8 64 128 1024 2048 Legend TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 Time constant register A_0 Time con...

Page 220: ...ontrol logic Legend TCORA_X Time constant register A_X TCORB_X Time constant register B_X TCNT_X Timer counter_X TCSR_X Timer control status register_X TCR_X Timer control register_X TICR Input captur...

Page 221: ...Clock select Internal bus Control logic Legend TCORA_A Time constant register A_A TCORB_A Time constant register B_A TCNT_A Timer counter_A TCSR_A Timer control status register_A TCR_A Timer control...

Page 222: ...Timer clock reset input TMIY ExTMIY TMCIY TMRIY Input External clock input external reset input for the counter TMR_Y Timer output TMOY Output Output controlled by compare match Timer output TMOX ExT...

Page 223: ...ster B_1 TCORB_1 Timer control register_1 TCR_1 Timer control status register_1 TCSR_1 TMR_Y Timer counter_Y TCNT_Y Time constant register A_Y TCORA_Y Time constant register B_Y TCORB_Y Timer control...

Page 224: ...nter_A TCNT_A Time constant register A_A TCORA_A Time constant register B_A TCORB_A Timer control register_A TCR_A Timer control status register_A TCSR_A Input capture register_A TICR_A Input capture...

Page 225: ...A in TCSR is set to 1 Note however that comparison is disabled during the T2 state of a TCORA write cycle The timer output from the TMO pin can be freely controlled by these compare match A signals an...

Page 226: ...rupt request CMIA is enabled or disabled when the CMFA flag in TCSR is set to 1 For TMR_X a CMIA interrupt does not occur irrespective of the value of this bit 0 CMFA interrupt request CMIA is disable...

Page 227: ...0 1 0 Increments at falling edge of internal clock 8 0 0 1 1 Increments at falling edge of internal clock 2 0 1 0 0 Increments at falling edge of internal clock 64 0 1 0 1 Increments at falling edge o...

Page 228: ...0 0 0 0 Disables clock input 0 0 1 0 Increments at 0 1 0 0 Increments at 2 0 1 1 0 Increments at 4 1 0 0 0 Disables clock input 0 0 0 1 Disables clock input 0 0 1 1 Increments at 2048 0 1 0 1 Increme...

Page 229: ...Increments at both rising and falling edges of external clock TMR_A 0 0 0 0 Disables clock input 0 0 1 0 Increments at 0 1 0 0 Increments at 2 0 1 1 0 Increments at 4 1 0 0 0 Disables clock input 0 0...

Page 230: ...H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 ADTE 0 R W A D Trigger Enable Enables or disables A D converter start requests by compare match A 0 A D converter start requests by co...

Page 231: ...1 overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 1 R Reserved This bit is always read as 1 and cannot be modified 3 2 OS3 OS2 0 0 R W R W Output Select 3 2 Th...

Page 232: ...Capture Interrupt Enable Enables or disables the ICF interrupt request ICIX when the ICF bit in TCSR_X is set to 1 0 ICF interrupt request ICIX is disabled 1 ICF interrupt request ICIX is enabled 3 2...

Page 233: ...1 then write 0 in OVF 4 ICF 0 R W Input Capture Flag Setting condition When a rising edge and falling edge is detected in the external reset signal in that order Clearing condition Read ICF when ICF...

Page 234: ...write 0 in OVF 4 ICIE 0 R W Input Capture Interrupt Enable Enables or disables the ICF interrupt request ICIA when the ICF bit in TCSR_A is set to 1 0 ICF interrupt request ICIA is disabled 1 ICF inte...

Page 235: ...1 then write 0 in OVF 4 ICF 0 R W Input Capture Flag Setting condition When a rising edge and falling edge is detected in the external reset signal in that order Clearing condition Read ICF when ICF...

Page 236: ...I TCRAB is set to 1 the contents of TCNT are transferred at the rising edge and falling edge of the external reset input TMRIX and TMRIA in that order The ICST bit is cleared to 0 when one capture ope...

Page 237: ...of TCNT at those points are captured into TICRR and TICRF respectively and the ICST bit is cleared to 0 Clearing condition When a rising edge followed by a falling edge is detected on TMRIX Setting co...

Page 238: ...e Initial Value R W Description 7 IOSX 0 R W TMR_X I O Select 0 Output to P67 TMOX and input from P60 TMIX 1 Output to PF6 ExTMOX and input from PF4 ExTMIX 6 IOSY 0 R W TMR_Y Output Enable 0 Output to...

Page 239: ...Capture Start Bit TMR_A has input capture registers TICRR_A and TICRF_A TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit When...

Page 240: ...h of TCORA and then set the CCLR0 bit to 1 2 Set the OS3 to OS0 bits in TCSR to B 0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCO...

Page 241: ...lock TCNT input clock TCNT N 1 N N 1 Figure 10 5 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N 1 N N 1 Figure 10 6 Count Timing for External Clock Input Both E...

Page 242: ...mer output when the output is set to toggle by a compare match A signal Compare match A signal Timer output pin Figure 10 8 Timing of Toggled Timer Output by Compare Match A Signal 10 5 4 Timing of Co...

Page 243: ...Figure 10 10 shows the timing of clearing the counter by an external reset input Clear signal External reset input pin TCNT N H 00 N 1 Figure 10 10 Timing of Counter Clear by External Reset Input 10...

Page 244: ...compare match the 16 bit counter TCNT_0 and TCNT_1 together is cleared when a 16 bit compare match occurs The 16 bit counter TCNT_0 and TCNT_1 together is also cleared when counter clear by the TMI0 p...

Page 245: ...ight bits of TCNT_Y are cleared The upper eight bits of TCNT_Y are also cleared when counter clear by the TMRIY pin has been set The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled and the l...

Page 246: ...set to 1 when an upper 8 bit compare match occurs The CMF flag in TCSR_A is set to 1 when a lower 8 bit compare match occurs Counter clear specification If the CCLR1 and CCLR0 bits in TCR_B have been...

Page 247: ...ICRF Input Capture Signal Input Timing Figure 10 12 shows the timing of the input capture operation TMRIX TMRIA Input capture signal TCNT_X TCNT_A n n n m M m N 1 N N n 1 TICRR TICRF Figure 10 12 Timi...

Page 248: ...0 5 Table 10 5 Input Capture Signal Selection TCONRI Bit 4 ICST Description 0 Input capture function not used 1 TMIX pin input selection TMRIA input capture input signal of TMR_A is selected according...

Page 249: ...TMR_B and TMR_A Channel Name Interrupt Source Interrupt Flag Interrupt Priority CMIA0 TCORA_0 compare match CMFA High CMIB0 TCORB_0 compare match CMFB TMR_0 OVI0 TCNT_0 overflow OVF CMIA1 TCORA_1 comp...

Page 250: ...clear signal TCNT Note TMR_A TMR_B N H 00 T1 T2 T3 TCNT write cycle by CPU Figure 10 14 Conflict between TCNT Write and Clear 10 10 2 Conflict between TCNT Write and Count Up If a count up occurs duri...

Page 251: ...and the compare match signal is disabled Address TCOR address Internal write signal TCNT TCOR N M TCOR write cycle by CPU TCOR write data N N 1 Compare match signal Disabled Note TMR_A TMR_B T1 T2 T3...

Page 252: ...nge from high to low level as shown in no 3 in table 10 9 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge and TCNT is incremented Erroneous incrementation can a...

Page 253: ...stop 4 Generated on the assumption that the switchover is a falling edge TCNT is incremented 10 10 6 Mode Setting with Cascaded Connection If the 16 bit count mode and compare match count mode are set...

Page 254: ...Rev 1 00 05 04 page 220 of 544...

Page 255: ...sed as an interval timer In interval timer operation an interval timer interrupt is generated each time the counter overflows A block diagram of the WDT_0 and WDT_1 is shown in figure 11 1 11 1 Featur...

Page 256: ...ister_1 TCNT_1 Timer counter_1 Notes 1 The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1 The internal reset signa...

Page 257: ...escriptions The WDT has the following registers To prevent accidental overwriting TCSR and TCNT have to be written to in a method different from normal registers For details refer to section 11 6 1 No...

Page 258: ...ally by the internal reset Clearing conditions When TCSR is read when OVF 1 2 then 0 is written to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the WDT is used as a wat...

Page 259: ...F 1 must be read at least twice TCSR_1 Bit Bit Name Initial Value R W Description 7 OVF 0 R W 1 Overflow Flag Indicates that TCNT has overflowed changes from H FF to H 00 Setting condition When TCNT o...

Page 260: ...0 Selects the clock source to be input to TCNT The overflow cycle for 10 MHz and SUB 32 768 kHz is enclosed in parentheses When PSS 0 000 2 frequency 51 2 s 001 64 frequency 1 64 ms 010 128 frequency...

Page 261: ...d the low level signal is simultaneously output from the RESO pin for 132 states as shown in figure 11 2 If the RST NMI bit is cleared to 0 when the TCNT overflows an NMI interrupt request is generate...

Page 262: ...Internal reset signal Legend WT IT TME OVF Overflow OVF 1 Timer mode select bit Timer enable bit Overflow flag Note After the OVF bit becomes 1 it is cleared to 0 by an internal reset The XRST bit is...

Page 263: ...When the TCNT overflows in interval timer mode an interval timer interrupt WOVI is requested at the same time the OVF bit of TCSR is set to 1 The timing is shown figure 11 4 TCNT value H 00 Time H FF...

Page 264: ...w signal internal signal OVF RESO signal Internal reset signal Figure 11 5 Output Timing of RESO signal 11 5 Interrupt Sources During interval timer mode operation an overflow generates an interval ti...

Page 265: ...ite address Therefore satisfy the relative condition shown in figure 11 6 to write to TCNT or TCSR To write to TCNT the upper bytes must contain the value H 5A and the lower bytes must contain the wri...

Page 266: ...between TCNT Write and Increment 11 6 3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating errors could occur in the incrementation Software m...

Page 267: ...eed mode and sub active or watch mode the counter does not display the correct value due to internal clock switching Specifically when transiting from high speed mode to sub active or watch mode that...

Page 268: ...Rev 1 00 05 04 page 234 of 544...

Page 269: ...ed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data The on chip baud rate generator allows any...

Page 270: ...us register SCMR Smart card mode register BRR Bit rate register Note The program development tool emulator does not support this function Figure 12 1 Block Diagram of SCI 12 2 Input Output Pins Table...

Page 271: ...nsfers the received serial data from RSR to RDR where it is stored After this RSR can receive the next data Since RSR and RDR function as a double buffer in this way continuous receive operations can...

Page 272: ...7 bits as the data length LSB first is fixed and the MSB of TDR is not transmitted in transmission In clocked synchronous mode a fixed data length of 8 bits is used 5 PE 0 R W Parity Enable enabled on...

Page 273: ...ction 12 3 9 Bit Rate Register BRR n is the decimal display of the value of n in BRR 12 3 6 Serial Control Register SCR SCR is a register that performs enabling or disabling of SCI transfer operations...

Page 274: ...details refer to section 12 5 Multiprocessor Communication Function 2 TEIE 0 R W Transmit End Interrupt Enable When this bit is set to 1 a TEI interrupt request is enabled 1 0 CKE1 CKE0 0 0 R W R W Cl...

Page 275: ...ading TDRE 1 6 RDRF 0 R W Receive Data Register Full Indicates that receive data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR...

Page 276: ...he TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character Clearing conditions When 0 is written to TDRE after reading TDRE 1 1 MPB 0 R Multiprocessor Bit...

Page 277: ...lid only when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Data Invert Specifies inversio...

Page 278: ...2 2 Relationships between N Setting in BRR and Bit Rate B Mode Bit Rate Error Asynchronous mode B 64 2 N 1 2n 1 106 Error B 64 2 N 1 2n 1 106 1 100 Clocked synchronous mode B 64 2 N 1 2n 1 106 Legend...

Page 279: ...255 0 00 2 64 0 16 300 1 103 0 16 1 127 0 00 1 129 0 16 600 0 207 0 16 0 255 0 00 1 64 0 16 1200 0 103 0 16 0 127 0 00 0 129 0 16 2400 0 51 0 16 0 63 0 00 0 64 0 16 4800 0 25 0 16 0 31 0 00 0 32 1 36...

Page 280: ...0 16 4800 0 38 0 16 0 39 0 00 0 47 0 00 0 51 0 16 9600 0 19 2 34 0 19 0 00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5...

Page 281: ...0 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 Table 12 5 Maximum Bit Rate with External Clock Input Asynchronous Mode MHz External Input Clock MHz Maximum Bit Rate bi...

Page 282: ...99 0 199 0 249 25k 0 39 0 79 0 99 50k 0 19 0 39 0 49 100k 0 9 0 19 0 24 250k 0 3 0 7 0 9 500k 0 1 0 3 0 4 1M 0 0 0 1 2 5M 0 0 5M Legend Blank Cannot be set Can be set but there will be a degree of err...

Page 283: ...ally stop bits high level In asynchronous serial communication the transmission line is usually held in the mark state high level The SCI monitors the transmission line and when it goes to the space s...

Page 284: ...ble 12 8 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit d...

Page 285: ...reception margin in asynchronous mode is determined by formula 1 below M 0 5 1 F L 0 5 F 100 Formula 1 2N 1 N D 0 5 Legend M Reception margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1...

Page 286: ...clock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the SCK pin The frequency of the clock...

Page 287: ...ialization completion Start initialization Set data transfer receive format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in BRR Clear TE and RE bits in SCR to...

Page 288: ...bit or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the data is transferred from...

Page 289: ...frame of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag t...

Page 290: ...set to 1 at this time an ERI interrupt request is generated 5 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to...

Page 291: ...ived 1 SCI initialization The RxD pin is automatically designated as the receive data input pin 2 3 Receive error processing and break detection If a receive error occurs read the ORER PER and FER fla...

Page 292: ...essing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0...

Page 293: ...nt When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose ID does not m...

Page 294: ...TEND 1 Break output Clear TDRE flag to 0 1 SCI initialization The TxD pin is automatically designated as the transmit data output pin After the TE bit is set to 1 a frame of 1s is output and transmis...

Page 295: ...t bit Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt handling rou...

Page 296: ...eck that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0...

Page 297: ...ror processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 12 13 Sample Multipr...

Page 298: ...n clock Both the transmitter and the receiver also have a double buffered structure so that the next transmit data can be written during transmission or the previous receive data can be read during re...

Page 299: ...er receive format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elapsed Set CKE1 and C...

Page 300: ...4 The SCI checks the TDRE flag at the timing for sending the last bit 5 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started 6 If...

Page 301: ...D 1 1 SCI initialization The TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write...

Page 302: ...finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Because the RXI inter...

Page 303: ...e RDRF flag from 0 to 1 can also be identified by an RXI interrupt 5 Serial reception continuation procedure Figure 12 19 Sample Serial Reception Flowchart 12 6 5 Simultaneous Serial Data Transmission...

Page 304: ...e error processing If a receive error occurs read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transmission reception cannot be resumed if the OR...

Page 305: ...pt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to...

Page 306: ...communication line at mark state until TE is set to 1 set both DDR and DR to 1 Since the TE bit is cleared to 0 at this point the TxD pin becomes an I O port and 1 is output from the TxD pin To send...

Page 307: ...e to TDR clear TDRE in this order and then start transmission To transmit data in a different transmission mode initialize the SCI first Figure 12 21 shows a sample flowchart for mode transition durin...

Page 308: ...ng to TDR and clearing TDRE to 0 after mode cancellation 2 Also clear TIE and TEIE to 0 when they are 1 3 Module stop watch sub active and sub sleep modes are included Figure 12 21 Sample Flowchart fo...

Page 309: ...e Initialized in software standby mode Figure 12 23 Pin States during Transmission in Clocked Synchronous Mode Internal Clock Start reception Reception 1 No No Yes Yes Read receive data in RDR Read RD...

Page 310: ...re 12 25 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins specify the SCK pins for input pull up the SCK port pins ex...

Page 311: ...in transmission I2 C bus format Wait function in master mode I2 C bus format A wait can be inserted by driving the SCL pin low after data transfer excluding acknowledgement The wait can be cleared by...

Page 312: ...tion 22 Electrical Characteristics SCL PS Noise canceler Bus state decision circuit Arbitration decision circuit Output data control circuit ICCR Clock control ICXR ICMR ICSR PGCTL ICDRS Address compa...

Page 313: ...L in SCL out SDA in SDA out Slave 1 SCL SDA SCL in SCL out SDA in SDA out Slave 2 SCL SDA SCL in SCL out SDA in SDA out Master This LSI SCL SDA VCC VCC SCL SDA VDD Figure 13 2 I2 C Bus Interface Conne...

Page 314: ...Symbol 1 Input Output Function SCL0 Input Output Serial clock input output pin of IIC_0 0 SDA0 Input Output Serial data input output pin of IIC_0 SCL1 Input Output Serial clock input output pin of IIC...

Page 315: ...n the ICE bit is set to 1 ICMR and ICDR can be accessed For details on the serial timer control register see section 3 2 3 Serial Timer Control Register STCR I2 C bus data register ICDR Slave address...

Page 316: ...ically from ICDRT to ICDRS following transmission of one frame of data using ICDRS When the ICDRE flag is 1 and the next transmit data writing is waited data is transferred automatically from ICDRT to...

Page 317: ...art condition the LSI operates as the slave device specified by the master device SAR can be accessed only when the ICE bit in ICCR is cleared to 0 Bit Bit Name Initial Value R W Description 7 6 5 4 3...

Page 318: ...the first frame received after a start condition the LSI operates as the slave device specified by the master device SARX can be accessed only when the ICE bit in ICCR is cleared to 0 Bit Bit Name In...

Page 319: ...ed SARX slave address ignored General call address recognized 1 0 I 2 C bus format SAR slave address ignored SARX slave address recognized General call address ignored 1 Clocked synchronous serial for...

Page 320: ...format 0 Data and the acknowledge bit are transferred consecutively with no wait inserted 1 After the fall of the clock for the final data bit 8 th clock the IRIC flag is set to 1 in ICCR and a wait s...

Page 321: ...frames If bits BC2 to BC0 are set to a value other than 000 the setting should be made while the SCL line is low The bit counter is initialized to 000 when a start condition is detected The value retu...

Page 322: ...1 kHz 125 kHz 156 kHz 0 1 0 0 80 62 5 kHz 100 kHz 125 kHz 0 1 0 1 100 50 0 kHz 80 0 kHz 100 kHz 0 1 1 0 112 44 6 kHz 71 4 kHz 89 3 kHz 0 1 1 1 128 39 1 kHz 62 5 kHz 78 1 kHz 1 0 0 0 56 89 3 kHz 143 k...

Page 323: ...Enable 0 Disables interrupts from the I 2 C bus interface to the CPU 1 Enables interrupts from the I2 C bus interface to the CPU 5 4 MST TRS 0 0 R W R W Master Slave Select Transmit Receive Select MS...

Page 324: ...at master mode TRS setting conditions 1 When 1 is written by software except for TRS clearing condition 3 2 When 1 is written in TRS after reading TRS 0 for TRS clearing condition 3 3 When 1 is receiv...

Page 325: ...of SCL high assuming that the start condition has been issued BBSY clearing condition When the SDA level changes from low to high under the condition of SCL high assuming that the stop condition has...

Page 326: ...ceive clock while no wait is inserted When a slave address is received after bus arbitration is lost the first frame after the start condition If 1 is received as the acknowledge bit when the ACKB bit...

Page 327: ...CDRS to ICDRR in receive mode and the ICDRF flag is set to 1 Clearing conditions When 0 is written in IRIC after reading IRIC 1 Note Only 0 can be written to clear the flag When with the I2 C bus form...

Page 328: ...Transmission end with ICDRE 1 1 1 1 0 0 0 0 0 0 0 0 ICDR write with the above state or after start condition detected 1 1 1 0 0 1 0 0 0 0 0 1 Automatic data transfer from ICDRT to ICDRS with the abov...

Page 329: ...l call address match in first frame SARX H 00 0 1 0 1 1 0 0 1 1 0 0 0 1 1 SARS match in first frame SAR SARX 0 1 1 0 0 0 1 Transmission end ACKE 1 and ACKB 1 0 1 1 0 0 1 0 1 0 0 1 Transmission end wit...

Page 330: ...read with the above state 0 0 1 0 0 1 0 2 0 0 0 1 Automatic data transfer from ICDRS to ICDRR with the above state 0 0 1 0 3 0 1 3 0 Stop condition detected Legend 0 0 state retained 1 1 state retain...

Page 331: ...er frame transfer completion Clearing conditions When 0 is written in STOP after reading STOP 1 When the IRIC flag is cleared to 0 5 IRTR 0 R W I 2 C Bus Interface Continuous Transfer Interrupt Reques...

Page 332: ...mode 3 AL 0 R W Arbitration Lost Flag Indicates that arbitration was lost in master mode Setting conditions When ALSL 0 If the internal SDA and SDA pin disagree at the rise of SCL in master transmit...

Page 333: ...r read from receive mode When 0 is written in AAS after reading AAS 1 In master mode 1 ADZ 0 R W General Call Address Recognition Flag In I 2 C bus format slave receive mode this flag is set to 1 if t...

Page 334: ...rom the bus line returned by the receiving device is read in transmission when TRS 1 In reception when TRS 0 the value set by internal software is read When this bit is written acknowledge data that i...

Page 335: ...l latch cleared 0111 IIC_0 and IIC_1 internal latches cleared 1 Invalid setting When a write operation is performed on these bits a clear signal is generated for the internal latch circuit of the corr...

Page 336: ...P 1 or ESTP 1 in slave mode 1 Disables IRIC flag setting and interrupt generation when the stop condition is detected 6 HNDS 0 R W Handshake Receive Operation Select Enables or disables continuous rec...

Page 337: ...is received successfully while ICDRF 0 at the rise of the 9th clock pulse 2 When ICDR is read successfully in receive mode after data was received while ICDRF 1 Clearing conditions When ICDR ICDRR is...

Page 338: ...e ICDRE 0 at the rise of the 9th clock pulse 2 When data is written to ICDR in transmit mode after data transmission was completed while ICDRE 1 Clearing conditions When data is written to ICDR ICDRT...

Page 339: ...0 When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL or when the SCL pin is driven low by another device 1 When the SDA pin state disagrees with the data...

Page 340: ...3 2 IIC0BS IIC0AS 0 0 R W R W IIC_0 Input Output Select B A Selects input output pins for IIC_1 channel IIC0BS IIC0AS 0 0 Selects P97 SDA0 and P52 SCL0 as IIC_0 I O pins 0 1 Selects PG4 ExSDAA and PG5...

Page 341: ...3 5 shows the I2 C bus timing The symbols used in figures 13 3 to 13 5 are explained in table 13 6 S A SLA 7 n R W DATA A 1 1 m 1 1 1 A A 1 P 1 Transfer bit count n 1 to 8 Transfer frame count m 1 S S...

Page 342: ...r from the slave device to the master device when R W is 1 or from the master device to the slave device when R W is 0 A Acknowledge The receiving device drives SDA low to acknowledge a transfer The s...

Page 343: ...errupt STOPIM HNDS ALIE ALSL FNC1 and FNC0 Set acknowledge bit ACKB Set ICMR Set ICCR Set IICE 1 in STCR Set SAR and SARX Set ICE 1 in ICCR Set ICXR Start transmit receive operation Set interrupt enab...

Page 344: ...atus of the SCL and SDA lines 7 Wait for 1 byte to be transmitted 10 Wait for 1 byte to be transmitted 11 Determine end of tranfer 12 Stop condition issuance 8 Test the acknowledge bit transferred fro...

Page 345: ...R The selected slave device i e the slave device with the matching slave address drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal 7 When one frame of data has been tran...

Page 346: ...6 5 8 7 1 2 9 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 ICDRE IRTR ICDRT Note Data write in ICDR prohibited SCL master output Start condition generation Slave address Data 1 Data 1...

Page 347: ...1 Bit 0 Bit 0 ICDRE IRTR ICDR SCL master output Start condition issuance Data 2 9 ICDR write 9 IRIC clear 12 IRIC clear 11 ACKB read 12 Set BBSY 1and SCP 0 Stop condition issuance IRIC A 10 7 Data 1...

Page 348: ...ICCR Clear IRIC flag in ICCR Clear IRIC flag in ICCR Set HNDS 1 in ICXR Set BBSY 0 and SCP 0 in ICCR IRIC 1 No Yes Yes Read ICDR No 4 Clear IRIC flag 1 Select receive mode 2 Start receiving The first...

Page 349: ...he rise of the 9th clock pulse setting the ICDRF IRIC and IRTR flags to 1 If the IEIC bit has been set to 1 an interrupt request is sent to the CPU The master device drives SCL low from the fall of th...

Page 350: ...e 13 11 Example of Operation Timing in Master Receive Mode MLS WAIT 0 HNDS 1 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 9 7 8 A A Bit 7 Bit 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IRIC ICDRF I...

Page 351: ...or a receive wait Set IRIC at the fall of the 8th clock or Wait for 1 byte to be received Set IRIC at the rise of the 9th clock 5 Read the receive data 6 Clear IRIC flag to end the wait insertion 15 C...

Page 352: ...mode Clear IRIC flag IRIC flag should be cleared to 0 after setting WAIT 0 11 Clear IRIC flag to end the wait insertion 12 Wait for 1 byte to be received Set IRIC at the rise of the 9th clock 9 Set T...

Page 353: ...ynchronization with the internal clock until the IRIC flag clearing At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1 indicating that one frame of data has...

Page 354: ...the IRIC flag to detect the end of reception 15 Clear the WAIT bit in CMR to cancel the wait mode Then clear the IRIC flag Clearing of the IRIC flag should be done while WAIT 0 If the WAIT bit is cle...

Page 355: ...RTR 1 13 IRTR 0 12 4 IRTR 1 4 IRTR 0 3 Figure 13 16 Example of Stop Condition Issuance Timing in Master Receive Mode MLS ACKB 0 WAIT 1 13 4 5 Slave Receive Operation In I2 C bus format slave receive m...

Page 356: ...receive mode 2 Read the receive data remaining unread 3 to 7 Wait for one byte to be received slave address R W 10 Read the receive data The first read is a dummy read 9 Set acknowledge data for the l...

Page 357: ...d slave transmit operation is performed When the slave address does not match receive operation is halted until the next start condition is detected 5 At the 9th clock pulse of the receive frame the s...

Page 358: ...DR read Interrupt request occurrence Figure 13 18 Example of Slave Receive Mode Operation Timing 1 MLS 0 HNDS 1 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 359: ...No No Yes No AAS 1 and ADZ 1 No No 1 Select slave receive mode 2 Read the receive data remaining unread 3 to 7 Wait for one byte to be received slave address R W Set IRIC at the rise of the 9th clock...

Page 360: ...KB bit as an acknowledge signal 6 At the rise of the 9th clock pulse the IRIC flag is set to 1 If the IEIC bit has been set to 1 an interrupt request is sent to the CPU If the AASX bit has been set to...

Page 361: ...ACKB 0 HNDS 0 Start condition detection SDA master output SDA slave output 2 1 4 3 6 5 2 1 4 3 6 5 8 7 9 8 7 9 8 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 ICDRF ICDRS ICDRR IRIC SC...

Page 362: ...lear IRIC in ICCR Read IRIC in ICCR Read ACKB in ICSR Set TRS 0 in ICCR Read ICDR Read IRIC in ICCR IRIC 1 Yes Yes No No IRIC 1 Yes No 1 2 If the slave address matches to the address in the first fram...

Page 363: ...leared to 0 to detect the end of transmission Processing from ICDR writing to the IRIC flag clearing should be performed continuously Prevent any other interrupt processing from being inserted 4 The m...

Page 364: ...flag is set to 1 If the IRIC flag has been set it is cleared to 0 SDA master output SDA slave output 2 1 2 1 4 3 6 5 8 7 9 9 8 Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICDRE ICDR I...

Page 365: ...zation with the internal clock Figures 13 25 to 13 27 show the IRIC set timing and SCL control SCL SDA IRIC User processing Clear IRIC 2 3 1 A 8 7 3 2 1 9 8 7 When WAIT 0 and FS 0 or FSX 0 I2C bus for...

Page 366: ...bus format wait inserted SCL SDA IRIC User processing Clear IRIC Write to ICDR transmit or read from ICDR receive 1 A 8 1 9 8 Clear IRIC a Data transfer ends with ICDRE 0 at transmission or ICDRF 0 at...

Page 367: ...erial format a Data transfer ends with ICDRE 0 at transmission or ICDRF 0 at reception SCL SDA IRIC User processing Clear IRIC Clear IRIC Write to ICDR transmit or read from ICDR receive 8 7 2 1 4 3 1...

Page 368: ...er consists of two cascaded latches and a match detector The SCL or SDA pin input signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches...

Page 369: ...ng flags in ICMR ICCR and ICSR The value of the ICMR bit counter BC2 to BC0 Generated interrupt sources interrupt sources transferred to the interrupt controller Notes on Initialization Interrupt flag...

Page 370: ...aring 2 Execute a stop condition issuance instruction write 0 to BBSY and SCP to clear the BBSY bit to 0 and wait for two transfer rate clock cycles 3 Re execute initialization of the internal state a...

Page 371: ...ws the timing of SCL and SDA outputs in synchronization with the internal clock Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance series resi...

Page 372: ...and fall times are under 1000 ns and 300 ns The I2 C bus interface SCL and SDA output timing is prescribed by tcyc as shown in table 13 8 However because of the rise and fall times the I2 C bus inter...

Page 373: ...cyc tSr High speed mode 300 100 400 625 700 Standard mode 1000 250 1300 2200 2500 tSDASO slave 1 tSCLL 3 12 tcyc 2 tSr High speed mode 300 100 1400 1 500 1 200 1 Standard mode 0 0 600 375 300 tSDAHO 3...

Page 374: ...RS cleared to 0 Note that if the receive data ICDR data is read in the interval between execution of the instruction for issuance of the stop condition writing of 0 to BBSY and SCP in ICCR and the act...

Page 375: ...Low 1 IRIC determination Start condition generation retransmission IRIC 1 Yes Clear IRIC in ICSR Read SCL pin Write transmit data to ICDR Set BBSY 1 SCP 0 ICSR 1 1 Wait for end of 1 byte transfer 2 D...

Page 376: ...L pin low is used the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low Stop condition generation SCL IRIC 1 SCL low de...

Page 377: ...ould be cleared after determining that the SCL is low as described below If the IRIC flag is cleared to 0 when WAIT 1 while the SCL is extending the high level time the SDA level may change before the...

Page 378: ...g conditions Read ICDR data that has been received so far or read write from to ICCR before starting the receive operation of the next slave address Monitor the BC2 to BC0 bit counter in ICMR when the...

Page 379: ...condition is input without the stop condition the effective TRS bit value remains 1 transmit mode internally and thus the acknowledge bit is not transmitted after the address has been received at the...

Page 380: ...re to follow the procedures below A When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation clear the ACKE bit in ICCR once to initi...

Page 381: ...sly set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode In multi master mode pay attention to the setting of the MST bit when a bus conflict may oc...

Page 382: ...Rev 1 00 05 04 page 348 of 544...

Page 383: ...e keyboard buffer controller 14 1 Features Conforms to PS 2 interface specifications Direct bus drive via the KCLK and KD pins Interrupt sources on completion of data reception and on detection of clo...

Page 384: ...buffer controller Table 14 1 Pin Configuration Channel Name Abbreviation I O Function KBC clock I O pin KCLK0 PS2AC I O KBC clock input output 0 KBC data I O pin KD0 PS2AD I O KBC data input output K...

Page 385: ...ins have port functions 1 The keyboard buffer controller is enabled for transmission and reception KCLK and KD signal pins are in the bus drive state 6 KCLKI 1 R W Keyboard Clock In Monitors the KCLK...

Page 386: ...KBF when KBF 1 then write 0 in KBF 1 Setting conditions When data has been received normally and has been transferred to KBBR while KBFSEL 1 keyboard buffer register full flag When a KCLK falling edge...

Page 387: ...ck I O pin is low 1 KBC clock I O pin is high 5 KDO 1 R W Keyboard Data Out Controls KBC data I O pin output 0 KBC data I O pin is low 1 KBC data I O pin is high 4 1 Reserved This bit is always read a...

Page 388: ...nly when KBF 1 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 0 0 0 0 0 0 0 0 R R R R R R R R Keyboard Data 7 to 0 8 bit read only data Initialized to H 00...

Page 389: ...ssion state Execute receive abort processing Error handling 1 Set the KBIOE bit to 1 in KBCRL 2 Read KBCRH and if the KCLKI and KDI bits are both 1 set the KBE bit receive enabled state 3 Detect the s...

Page 390: ...10 11 7 0 1 KB0 KB1 1 2 3 4 5 6 Figure 14 4 Receive Timing 14 4 2 Transmit Operation In a transmit operation KCLK clock is an output on the keyboard side and KD data is an output on the chip system s...

Page 391: ...LKI and KDI bits are both 1 write 0 in the KCLKO bit set I O inhibit 3 Write 0 in the KBE bit prohibit KBBR receive operation 4 Write 0 in the KDO bit set start bit 5 Write 1 in the KCLKO bit clear I...

Page 392: ...Error handling To receive operation or transmit operation Keyboard side in data transmission state Execute receive abort processing 2 7 8 Figure 14 5 Sample Transmit Processing Flowchart 2 1 0 1 0 1...

Page 393: ...ceive abort request Retransmit command transmission data KBE 0 disable KBBR reception and clear receive counter Set start bit KDO 0 Clear I O inhibit KCLKO 1 Transmit data To transmit operation KBE 0...

Page 394: ...he data is transmitted Figure 14 7 Sample Receive Abort Processing Flowchart 2 Keyboard side monitors clock during receive operation transmit operation as seen from keyboard and aborts receive operati...

Page 395: ...caled by 1 N in medium speed mode when the operating mode is active mode Figure 14 9 KCLKI and KDI Read Timing 14 4 5 KCLKO and KDO Write Timing Figure 14 10 shows the KLCKO and KDO write timing and t...

Page 396: ...d the KCLK pin states KCLK pin Internal KCLK Falling edge signal RXCR3 to RXCR0 KCLK output KBF 11th fall Automatic I O inhibit B 0000 B 1010 Note The clock shown here is scaled by 1 N in medium speed...

Page 397: ...ive timing N 1 N 2 N KCLK pin Note The clock shown here is scaled by 1 N in medium speed mode when the operating mode is active mode KD pin Internal KCLK KCLKI Falling edge signal RXCR3 to RXCR0 Inter...

Page 398: ...KBE 0 KBBR reception disabled Interrupt handling Clear KBF KCLK pin fall detected KBFSEL 0 KBIE 1 KCLK falling edge interrupts enabled Yes No KCLK pin state KBF bit Interrupt generated Interrupt gene...

Page 399: ...low when the KBIOE bit is set to 1 the edge detection circuit operates and the KCLK falling edge is detected If the KBFSEL bit and KBE bit are both 0 at this time the KBF bit is set Figure 14 14 show...

Page 400: ...ffer controller operation can be enabled or disabled using the module stop control register The initial setting is for keyboard buffer controller operation to be halted Register access is enabled by c...

Page 401: ...egister sets comprising data and status registers The basic register set comprises three bytes an input register IDR output register ODR and status register STR Channels 1 and 2 have fixed I O address...

Page 402: ...Cycle detection Serial parallel conversion Serial parallel conversion Address match SYNC output Parallel serial conversion Control logic Internal interrupt control HISEL Legend HICR0 to HICR3 Host int...

Page 403: ...put output 1 Serialized host interrupt request signal synchronized with LCLK SMI IRQ1 IRQ6 IRQ9 to IRQ12 LSCI general output LSCI PB1 Output 1 2 General output LSMI general output LSMI PB0 Output 1 2...

Page 404: ...3 HICR3 LPC channel 3 address registers LADR3H LADR3L Input data register 1 IDR1 Output data register 1 ODR1 Status register 1 STR1 Input data register 2 IDR2 Output data register 2 ODR2 Status regis...

Page 405: ...terface function in single chip mode When the host interface is enabled one of the three bits is set to 1 processing for data transfer between the slave processor this LSI and the host processor is pe...

Page 406: ...lized to 1 1 Fast A20 gate function enabled GA20 pin output is open drain external VCC pull up resistor required 3 SDWNE 0 R W LPC Software Shutdown Enable Controls host interface shutdown For details...

Page 407: ...output is open drain and an external pull up resistor is needed to pull the output up to VCC When the LSMI output function is used the DDR bit for PB0 must not be set to 1 LSMIE LSMIB 0 x LSMI output...

Page 408: ...bort of transfer cycle subject to processing Normal termination of transfer cycle subject to processing 1 Host interface is performing transfer cycle processing Setting condition Match of cycle type a...

Page 409: ...re reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame 1 SERIRQ transfer processing in progress Setting condition Start of SERIRQ transfer frame 4 LRSTB 0 LPC Software Re...

Page 410: ...reset LPC hardware shutdown LPC hardware shutdown release rising edge of LPCPD signal when SDWNE 0 1 LPC software shutdown state Setting condition Writing 1 after reading SDWNB 0 2 PMEB 0 R W PME Outp...

Page 411: ...C hardware reset occurs 0 Clearing conditions Writing 0 after reading LRST 1 1 Setting condition LRESET pin falling edge detection 5 SDWN 0 R W LPC Shutdown Interrupt Flag This bit is a flag that gene...

Page 412: ...2 receive completed interrupt requests enabled 1 IBFIE1 0 R W IDR1 Receive Completion Interrupt Enable Enables or disables IBFI1 interrupt to the slave processor this LSI 0 Input data register IDR1 re...

Page 413: ...f LADR3 When determining an IDR3 ODR3 or STR3 address match bit 0 of LADR3 is regarded as 0 and the value of bit 2 is ignored When determining a TWR0 to TWR15 address match bit 4 of LADR3 is inverted...

Page 414: ...sor this LSI and 8 bit write only registers for the host processor The registers selected from the host according to the I O address are shown in the following table For information on IDR3 selection...

Page 415: ...sor and a read only register for the host processor When the host and slave processors begin a write after the respective TWR0 registers have been written to access right arbitration for simultaneous...

Page 416: ...by User The user can use this bit as necessary 1 IBF1 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR This bit is an internal interrupt source to the slave processor this LSI IB...

Page 417: ...when the host processor writes to IDR This bit is an internal interrupt source to the slave processor this LSI IBF is cleared to 0 when the slave processor reads IDR The IBF1 flag setting and clearin...

Page 418: ...host processor reads TWR15 using I O read cycle or the slave processor writes 0 to the OBF3B bit 1 Setting condition When the slave processor writes to TWR15 5 MWMF 0 R R Master Write Mode Flag Set t...

Page 419: ...rupt source to the slave processor this LSI IBF is cleared to 0 when the slave processor reads IDR The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used For detail...

Page 420: ...t to 1 when the host processor writes to IDR This bit is an internal interrupt source to the slave processor this LSI IBF is cleared to 0 when the slave processor reads IDR The IBF1 flag setting and c...

Page 421: ...rame 6 SELREQ 0 R W Start Frame Initiation Request Select Selects whether start frame initiation is requested when one or more interrupt requests are cleared or when all interrupt requests are cleared...

Page 422: ...rrupt request by setting OBF3B to 1 is enabled When IEDIR 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE3B 0 3 SMIE3A 0 R W Host SMI Interrupt Enable 3A Enables or di...

Page 423: ...0 1 When IEDIR 0 Host SMI interrupt request by setting OBF2 to 1 is enabled When IEDIR 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE2 0 1 IRQ12E1 0 R W Host IRQ12 In...

Page 424: ...1 to 1 is enabled Setting condition Writing 1 after reading IRQ1E1 0 SIRQCR1 R W Bit Bit Name Initial Value Slave Host Description 7 IRQ11E3 0 R W Host IRQ11 Interrupt Enable 3 Enables or disables a h...

Page 425: ...errupt request by setting OBF3A to 1 is enabled When IEDIR 1 Host IRQ10 interrupt is requested Setting condition Writing 1 after reading IRQ10E3 0 5 IRQ9E3 0 R W Host IRQ9 Interrupt Enable 3 Enables o...

Page 426: ...t request by setting OBF3A to 1 is enabled When IEDIR 1 Host IRQ6 interrupt is requested Setting condition Writing 1 after reading IRQ6E3 0 3 IRQ11E2 0 R W Host IRQ11 Interrupt Enable 2 Enables or dis...

Page 427: ...terrupt request by setting OBF2 to 1 is enabled When IEDIR 1 Host IRQ10 interrupt is requested Setting condition Writing 1 after reading IRQ10E2 0 1 IRQ9E2 0 R W Host IRQ9 Interrupt Enable 2 Enables o...

Page 428: ...when OBF2 is set by an ODR2 write 0 Host IRQ6 interrupt request by OBF2 and IRQ6E2 is disabled Clearing conditions Writing 0 to IRQ6E2 LPC hardware reset LPC software reset Clearing OBF2 to 0 when IE...

Page 429: ...n STR3 are status bits of the host interface 1 When TWRE 1 Bits 7 to 4 in STR3 are status bits of the host interface When TWRE 0 Bits 7 to 4 in STR3 are user bits 6 5 4 3 2 1 0 SELIRQ11 SELIRQ10 SELIR...

Page 430: ...llowing procedure to activate the host interface after a reset release 1 Read the signal line status and confirm that the LPC module can be connected Also check that the LPC module is initialized inte...

Page 431: ...register IDR ODR STR TWR the host interface enters the busy state it returns to the idle state by output of a state count 12 turnaround Register and flag changes are made at this timing so in the eve...

Page 432: ...LCLK TAR Sync Cycle type direction and size Slave must stop driving Too many Syncs cause timeout Master will drive high Figure 15 3 Abort Mechanism 15 4 3 A20 Gate The A20 gate signal can mask address...

Page 433: ...ipulate the output from this pin by sending commands and data This function is only available via the IDR1 register The host interface decodes commands input from the host When an H D1 host command is...

Page 434: ...data 1 0 1 1 0 Command other than H FF and H D1 1 Q 1 Turn on sequence abbreviated form 1 H D1 command 0 Q 0 0 data 2 0 0 1 0 Command other than H FF and H D1 1 Q 0 Turn off sequence abbreviated form...

Page 435: ...her hand the LPC software shutdown state cannot be cleared at the same time as the rise of the LPCPD signal Taking these points into consideration the following operating procedure uses a combination...

Page 436: ...put Needed to clear shutdown state Legend O Pin that is shutdown by the shutdown function Pin that is shutdown only when the LPC function is selected by register setting Pin that is not shutdown In th...

Page 437: ...lized 0 Can be set cleared Can be set cleared SDWN flag Initialized 0 Initialized 0 Can be set cleared LRSTB bit Initialized 0 HR 0 SR 1 0 can be set SDWNB bit Initialized 0 Initialized 0 HS 0 SS 1 SD...

Page 438: ...05 04 page 404 of 544 Figure 15 5 shows the timing of the LPCPD and LRESET signals LPCPD LRESET LAD3 LAD0 LFRAME LCLK At least 30 s At least 100 s At least 60 s Figure 15 5 Power Down State Terminatio...

Page 439: ...e IRQ0 frame IRQ1 frame IRQ2 frame SL or H H R T R S T R S T R S T IRQ15 Host controller None None SERIRQ Driver LCLK START STOP IOCHCK frame Stop frame Next cycle IRQ14 frame IRQ15 frame R S T R S T...

Page 440: ...op Host Undefined First 1 or more idle states then 2 or 3 states 0 driven by host 2 states Quiet mode next 3 states Continuous mode next There are two modes continuous mode and quiet mode for serializ...

Page 441: ...initiated by the host With SERIRQ in quiet mode when a host interrupt request is generated the CLKRUN signal is driven and a clock LCLK restart request is sent to the host The timing for this operatio...

Page 442: ...IRQ10 HIRQ11 and HIRQ12 The host interface can request seven kinds of host interrupt by means of SERIRQ HIRQ1 and HIRQ12 are used on LPC channel 1 only while SMI HIRQ6 HIRQ9 HIRQ10 and HIRQ11 can be r...

Page 443: ...m bit SMIE3A and writes 1 writes to TWR15 then reads 0 from bit SMIE3B and writes 1 Internal CPU writes 0 to bit SMIE2 or host reads ODR2 writes 0 to bit SMIE3A or host reads ODR3 writes 0 to bit SMIE...

Page 444: ...ter CPU ODR1 write Write 1 to IRQ1E1 OBF1 0 Yes No No Yes All bytes transferred SERIRQ IRQ1 output SERIRQ IRQ1 source clearance Interrupt initiation ODR1 read Hardware operation Software operation Fig...

Page 445: ...STR must be followed to avoid data contention For example if the host and slave processor both try to access IDR or ODR at the same time the data will be corrupted To prevent simultaneous accesses IB...

Page 446: ...4 ODR3 H A24A H 3FD0 STR3 H A24E H 3FD4 TWR0MW H A250 H 3FC0 TWR0SW H A250 H 3FC0 TWR1 H A251 H 3FC1 TWR2 H A252 H 3FC2 TWR3 H A253 H 3FC3 TWR4 H A254 H 3FC4 TWR5 H A255 H 3FC5 TWR6 H A256 H 3FC6 TWR7...

Page 447: ...age range can be specified using the reference power supply voltage pin AVref as an analog reference voltage Conversion time 13 4 s per channel at 10 MHz operation Two kinds of operating modes Single...

Page 448: ...S R A D C R A D D R D A D D R C A D D R B A D D R A Successive approximations register Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data regi...

Page 449: ...r Table 16 1 Pin Configuration Pin Name Symbol I O Function Analog power supply pin AVCC Input Analog block power supply and reference voltage Analog ground pin AVSS Input Analog block ground and refe...

Page 450: ...each channel are shown in table 16 2 The converted 10 bit data is stored to bits 15 to 6 The lower 6 bit data is always read as 0 The data bus between the CPU and the A D converter is 8 bit width The...

Page 451: ...it to 1 starts A D conversion Clearing this bit to 0 stops A D conversion In single mode this bit is cleared to 0 automatically when conversion on the specified channel ends In scan mode conversion co...

Page 452: ...d Note Only 0 can be written for clearing the flag 16 3 3 A D Control Register ADCR ADCR enables A D conversion started by an external trigger signal Bit Bit Name Initial Value R W Description 7 6 TRG...

Page 453: ...On completion of A D conversion the ADF bit in ADCSR is set to 1 If the ADIE bit is set to 1 at this time an ADI interrupt request is generated 4 The ADST bit remains set to 1 during A D conversion Wh...

Page 454: ...r A D conversion ends 5 Steps 2 to 4 are repeated as long as the ADST bit remains set to 1 When the ADST bit is cleared to 0 A D conversion stops After that if the ADST bit is set to 1 A D conversion...

Page 455: ...CONV includes tD and the input sampling time tSPL The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in...

Page 456: ...4 External Trigger Input Timing A D conversion can be externally triggered When the TRGS1 and TRGS0 bits are set to B 11 in ADCR external trigger input is enabled at the ADTRG pin A falling edge at th...

Page 457: ...t voltage value from the ideal A D conversion characteristic when the digital output changes from the minimum voltage value B 0000000000 H 000 to B 0000000001 H 001 see figure 16 6 Full scale error Th...

Page 458: ...on characteristic Analog input voltage H 002 H 003 H 004 H 3FD H 3FE H 3FF Figure 16 5 A D Conversion Accuracy Definitions FS Offset error Nonlinearity error Actual A D conversion characteristic Analo...

Page 459: ...rce impedance is ignored However since a low pass filter effect is obtained in this case it may not be possible to follow an analog signal with a large differential coefficient e g voltage fluctuation...

Page 460: ...ersely affecting A D conversion values Also digital circuitry must be isolated from the analog input signals AN0 to AN5 analog reference voltage AVref and analog power supply AVCC by the analog ground...

Page 461: ...To A D converter AN0 to AN5 10 k Note Values are reference values Figure 16 9 Equivalent Circuit of Analog Input Pin 16 7 6 Module Stop Mode Setting A D converter operation can be enabled or disabled...

Page 462: ...Rev 1 00 05 04 page 428 of 544...

Page 463: ...th byte data and word data The on chip RAM can be enabled or disabled by means of the RAME bit in the system control register SYSCR For details on SYSCR refer to section 3 2 2 System Control Register...

Page 464: ...Rev 1 00 05 04 page 430 of 544...

Page 465: ...block must be erased in turn Programming erase time It takes 10 ms typ to program the flash memory 128 bytes at a time 80 s typ per 1 byte Erasing one block takes 100 ms typ Reprogramming capability T...

Page 466: ...ng a PROM programmer Bus interface controller Flash memory 64 Kbytes Operating mode Internal address bus Internal data bus 16 bits Mode pin FLMCR2 EBR1 EBR2 FLMCR1 Legend FLMCR1 Flash memory control r...

Page 467: ...ram mode RES 0 RES 0 FLSHE 1 SWE 1 FLSHE 0 SWE 0 1 2 R E S 0 MD1 1 RES 0 Boot mode On board programming mode User program mode User mode on chip ROM enabled Reset state Programmer mode Notes Only make...

Page 468: ...uld prepare the programming control program and new application program beforehand in the host 2 SCI communication check When boot mode is entered the boot program in this LSI originally incorporated...

Page 469: ...gram 1 Initial state 1 The program that will transfer the programming erase control program from flash memory to on chip RAM should be written into the flash memory by the user beforehand 2 The progra...

Page 470: ...se unit 8 Kbytes H 000000 H 000001 H 000002 H 00007F H 0003FF H 00047F H 00087F H 000C7F H 00107F H 007FFF H 00807F H 00BFFF H 0007FF H 000BFF H 000FFF H 00C07F H 00DFFF H 00E07F H 00FFFF Programming...

Page 471: ...g mode P90 Input Sets this LSI s operating mode TxD1 Output Serial transmit data output RxD1 Input Serial receive data input 18 5 Register Descriptions The flash memory has the following registers To...

Page 472: ...n this bit is cleared to 0 the EV PV E and P bits in this register the ESU and PSU bits in FLMCR2 and all EBR1 and EBR2 bits cannot be set to 1 Do not clear these bits and SWE to 0 simultaneously 5 4...

Page 473: ...ndicates that an error has occurred during flash memory programming erasing When this bit is set to 1 flash memory goes to the error protection state For details see section 18 9 3 Error Protection 6...

Page 474: ...7 0 R W When this bit is set to 1 8 Kbytes of EB7 H 00E000 to H 00FFFF are to be erased 6 EB6 0 R W When this bit is set to 1 8 Kbytes of EB6 H 00C000 to H 00DFFF are to be erased 5 EB5 0 R W When thi...

Page 475: ...vanced Single chip mode 1 0 Enabled 64 Kbytes Mode 3 Normal Single chip mode 1 1 Enabled 56 Kbytes 18 7 On Board Programming Modes An on board programming mode is used to perform on chip flash memory...

Page 476: ...of bit rate adjustment The host should confirm that this adjustment end indication H 00 has been received normally and transmit one H 55 byte to this LSI If reception could not be performed normally i...

Page 477: ...to on chip RAM and starts execution H 00 H 00 H 00 H 00 H 55 Transmits data H 55 when data H 00 is received error free Boot program erase error H FF H AA Receives data H AA Receives data H AA H AA Ech...

Page 478: ...area and area which is not used cannot be used until a transition is made to the execution state for the programming control program transferred to RAM Note that the contents of the boot program area...

Page 479: ...elf cannot be read during programming erasing transfer the user program erase control program to on chip RAM as like in boot mode Figure 18 8 shows a sample procedure for programming erasing in user p...

Page 480: ...ch programming has already been performed 2 Programming should be carried out 128 bytes at a time A 128 byte data transfer must be performed even if writing fewer than 128 bytes In this case H FF data...

Page 481: ...write pulse Additional programming 128 byte data verification completed Successively write 128 byte data from additional programming data area in RAM to flash memory Reprogram Data Computation Table R...

Page 482: ...turn 3 The time during which the E bit is set to 1 is the flash memory erase time 4 The watchdog timer WDT is set to prevent overprogramming due to program runaway etc An overflow cycle of approximat...

Page 483: ...ar EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT End of erasing 1 Verify data all 1 Last address of block All erase blocks erased Erase failure Clear SWE bit in FLMCR1 n N NG NG NG NG OK OK OK...

Page 484: ...bit in FLMCR1 to 0 When software protection is in effect setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode By setting the erase block registers 1 and 2 EBR1 an...

Page 485: ...ecution 1 1 If an interrupt is generated during programming erasing operation in accordance with the program erase algorithm is not guaranteed 2 CPU runaway may occur because normal vector reading can...

Page 486: ...a discrete flash memory Use a PROM programmer that supports the Renesas 64 Kbyte flash memory on chip MCU device Figure 18 11 shows a memory map in programmer mode Note Set the programming voltage of...

Page 487: ...ory Do not set clear the SWE bit during program execution in the flash memory An interval of at least 100 s is necessary between program execution or data reading in flash memory and SWE bit clearing...

Page 488: ...Rev 1 00 05 04 page 454 of 544...

Page 489: ...er clock select circuit Subclock input circuit Waveform forming circuit EXTAL XTAL EXCL 2 to 32 SUB WDT_1 count clock System clock to pin Internal clock to peripheral modules Bus master clock to CPU F...

Page 490: ...e 19 3 shows the equivalent circuit of a crystal resonator A resonator having the characteristics given in table 19 2 should be used A crystal resonator with frequency identical to that of the system...

Page 491: ...ck should be set to high in standby mode subactive mode subsleep mode and watch mode External clock input conditions are shown in table 19 3 The frequency of the external clock should be the same as t...

Page 492: ...a function to adjust the waveform of the external clock input that is input to the EXTAL pin When a specified clock signal is input to the EXTAL pin internal clock signal output is determined after t...

Page 493: ...circuit is valid when the oscillating frequency is 5 MHz or more It corrects the duty of a clock that is output from the oscillator and generates the system clock 19 3 Medium Speed Clock Divider The m...

Page 494: ...ble 19 5 Subclock Input Conditions Vcc 3 0 to 3 6 V Item Symbol Min Typ Max Unit Measurement Condition Subclock input pulse width low level tEXCLL 15 26 s Subclock input pulse width high level tEXCLH...

Page 495: ...eristics of the resonator are closely related to the board design by the user use the example of resonator connection in this document for only reference be sure to use an resonator that has been suff...

Page 496: ...Rev 1 00 05 04 page 462 of 544...

Page 497: ...PU and on chip peripheral modules other than TMR_0 TMR_1 WDT_0 and WDT_1 stop operating Watch mode The CPU and on chip peripheral modules other than WDT_1 stop operating Software standby mode Clock os...

Page 498: ...Selects the wait time for clock stabilization from clock oscillation start when canceling software standby mode watch mode or subactive mode Select a wait time of 8 ms oscillation stabilization time o...

Page 499: ...fication 20 1 2 Low Power Control Register LPWRCR LPWRCR controls power down modes Bit Bit Name Initial Value R W Description 7 DTON 0 R W Direct Transfer On Flag Specifies the operating mode to be en...

Page 500: ...eed mode 1 Shifts to subsleep mode or watch mode When watch mode is cancelled 0 Shifts to high speed mode 1 Shifts to subactive mode 5 NESEL 0 R W Noise Elimination Sampling Frequency Select Selects t...

Page 501: ...1 2 R W 1 MSTP9 1 R W A D converter 0 MSTP8 1 R W 8 bit timers TMR_X TMR_Y Notes 1 Do not set this bit to 1 2 Do not clear this bit to 0 MSTPCRL Bit Bit Name Initial Value R W Corresponding Module 7...

Page 502: ...n handling SLEEP instruction SLEEP instruction External interrupt 3 Any interrupt SLEEP instruction SLEEP instruction SLEEP instruction Interrupt 1 LSON bit 0 Interrupt 2 Interrupt 1 LSON bit 1 STBY p...

Page 503: ...nctioning Functioning Functioning Functioning Halted WDT_1 Subclock operation WDT_0 Functioning TMR_0 TMR_1 Subclock operation Subclock operation FRT TMR_X TMR_Y TMR_A TMR_B IIC_0 IIC_1 LPC Functionin...

Page 504: ...uted when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0 a transition is made to sleep mode When sleep mode is cleared by an interrupt medium speed mode is restored W...

Page 505: ...tion is executed while the SSBY bit in SBYCR is set to 1 the LSON bit in LPWRCR is cleared to 0 and the PSS bit in TCSR WDT_1 is cleared to 0 In software standby mode the CPU on chip peripheral module...

Page 506: ...nsition is made to software standby mode at the falling edge of the NMI pin and software standby mode is cleared at the rising edge of the NMI pin In this example an NMI interrupt is accepted with the...

Page 507: ...ow Do not change the state of the mode pins MD1 and MD0 while this LSI is in hardware standby mode Hardware standby mode is cleared by the STBY pin input or the RES pin input When the STBY pin is driv...

Page 508: ...d to 0 or to subactive mode when the LSON bit is set to 1 When a transition is made to high speed mode a stable clock is supplied to the entire LSI and interrupt exception handling starts after the ti...

Page 509: ...S pin input or the STBY pin input When an interrupt occurs subsleep mode is exited and interrupt exception handling starts In the case of an IRQ0 to IRQ7 interrupt subsleep mode is not exited if the c...

Page 510: ...the SSBY bit in SBYCR set to 1 the DTON bit in LPWRCR cleared to 0 and the PSS bit in TCSR WDT_1 set to 1 the CPU exits subactive mode and a transition is made to watch mode When the SLEEP instruction...

Page 511: ...11 Direct Transitions The CPU executes programs in three modes high speed medium speed and subactive When a direct transition is made from high speed mode to subactive mode there is no interruption of...

Page 512: ...etained in software standby mode Therefore when a high level is output the current consumption is not reduced by the amount of current to support the high level output 20 12 2 Current Consumption when...

Page 513: ...lumn The bit number in the bit name column indicates that the whole register is allocated as a counter or for holding data 16 bit registers are indicated from the bit on the MSB side 3 Register States...

Page 514: ...constant register B_A TCORB_A 8 H FE07 TMR_A 8 3 Timer counter_B TCNT_B 8 H FE08 TMR_B 8 3 Timer counter_A TCNT_A 8 H FE09 TMR_A 8 3 Timer input select register_B TISR_B 8 H FE0A TMR_B 8 3 Input capt...

Page 515: ...2D LPC 8 3 Bidirectional data register 14 TWR14 8 H FE2E LPC 8 3 Bidirectional data register 15 TWR15 8 H FE2F LPC 8 3 Input data register 3 IDR3 8 H FE30 LPC 8 3 Output data register 3 ODR3 8 H FE31...

Page 516: ...ster PFPIN 8 H FE4B read PORT 8 3 Port F data direction register PFDDR 8 H FE4B write PORT 8 3 Port C output data register PCODR 8 H FE4C PORT 8 3 Port D output data register PDODR 8 H FE4D PORT 8 3 P...

Page 517: ...nterrupt control register A ICRA 8 H FEE8 INT 8 2 Interrupt control register B ICRB 8 H FEE9 INT 8 2 Interrupt control register C ICRC 8 H FEEA INT 8 2 IRQ status register ISR 8 H FEEB INT 8 2 IRQ sen...

Page 518: ...ond slave address register_1 SARX_1 8 H FF8E IIC_1 8 2 I 2 C bus mode register_1 ICMR_1 8 H FF8F IIC_1 8 2 Slave address register_1 SAR_1 8 H FF8F IIC_1 8 2 Timer interrupt enable register TIER 8 H FF...

Page 519: ...ort A data direction register PADDR 8 H FFAB PORT 8 2 Port 1 pull up MOS control register P1PCR 8 H FFAC PORT 8 2 Port 2 pull up MOS control register P2PCR 8 H FFAD PORT 8 2 Port 3 pull up MOS control...

Page 520: ...r control register_0 TCR_0 8 H FFC8 TMR_0 8 2 Timer control register_1 TCR_1 8 H FFC9 TMR_1 8 2 Timer control status register_0 TCSR_0 8 H FFCA TMR_0 8 2 Timer control status register_1 TCSR_1 8 H FFC...

Page 521: ...data register DL ADDRDL 8 H FFE7 A D converter 8 2 A D control status register ADCSR 8 H FFE8 A D converter 8 2 A D control register ADCR 8 H FFE9 A D converter 8 2 Timer control status register_1 TCS...

Page 522: ...FFF4 TMR_X 16 2 Timer counter_Y TCNT_Y 8 H FFF4 TMR_Y 16 2 Timer constant register C TCORC 8 H FFF5 TMR_X 16 2 Timer input select register TISR 8 H FFF5 TMR_Y 16 2 Timer constant register A_X TCORA_X...

Page 523: ...t 3 Bit 2 Bit 1 Bit 0 TCNT_B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNT_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TISR_B IS TICRR_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TI...

Page 524: ...R15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STR3 2 IBF3B OBF3B MWMF SWMF C D3 DBU32 IB...

Page 525: ...C2ODR PC1ODR PC0ODR PDODR PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR PCPIN PC7PIN PC6PIN PC5PIN PC4PIN PC3PIN PC2PIN PC1PIN PC0PIN PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR P...

Page 526: ...2 SYSTEM EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FLASH SBYCR SSBY STS2 STS1 STS0 SCK2 SCK1 SCK0 LPWRCR DTON LSON NESEL EXCLE MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MS...

Page 527: ...Bit 11 Bit 10 Bit 9 Bit 8 OCRARH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ICRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OCRARL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICR...

Page 528: ...DR P43DDR P42DDR P41DDR P40DDR P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR P4DR P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR P5DDR P52DDR P51DDR P50DDR P6DDR P67DDR P66DDR P65DDR P64DDR P6...

Page 529: ...OE5 OE4 OE3 OE2 OE1 OE0 PWDPRA OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 PWSL PWCKE PWCKS RS3 RS2 RS1 RS0 PWDR0 to PWDR7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM ICCR_0 ICE IEIC MST TRS ACKE BBSY IR...

Page 530: ...5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_Y KMIMRA KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 INT TICRF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_X TCORB_Y Bit 7 Bit 6 Bit 5 Bit...

Page 531: ...ialized TCORB_B Initialized Initialized TCORB_A Initialized Initialized TCNT_B Initialized Initialized TCNT_A Initialized Initialized TISR_B Initialized Initialized TICRR_A Initialized Initialized TIC...

Page 532: ...TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 Initialized Initialized LADR3H Initialized Initialized LADR3L Initialized Initialized SIRQCR0 Initialized Initialized SIRQCR1 Initialized Initialized IDR1...

Page 533: ...itialized Initialized KBCRL_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized KBBR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initial...

Page 534: ...Initialized Initialized Initialized Initialized FLASH SBYCR Initialized Initialized LPWRCR Initialized Initialized MSTPCRH Initialized Initialized MSTPCRL Initialized Initialized SYSTEM SMR_1 Initiali...

Page 535: ...L Initialized Initialized TCR Initialized Initialized TOCR Initialized Initialized ICRAH Initialized Initialized OCRARH Initialized Initialized FRT ICRAL Initialized Initialized OCRARL Initialized Ini...

Page 536: ...lized Initialized P3DDR Initialized Initialized P4DDR Initialized Initialized P3DR Initialized Initialized P4DR Initialized Initialized P5DDR Initialized Initialized P6DDR Initialized Initialized P5DR...

Page 537: ...d ICMR_0 Initialized Initialized SAR_0 Initialized Initialized ADDRAH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRAL Initialized Initialized Initialized Ini...

Page 538: ...d Initialized PORT TICRR Initialized Initialized TMR_X TCORA_Y Initialized Initialized TMR_Y KMIMRA Initialized Initialized INT TICRF Initialized Initialized TMR_X TCORB_Y Initialized Initialized TMR_...

Page 539: ...FE03 TCSR_A H FE04 TCORA_B H FE05 TCORA_A H FE06 TCORB_B H FE07 TCORB_A H FE08 TCNT_B H FE09 TCNT_A H FE0A TISR_B H FE0C TICRR_A H FE0D TICRF_A H FE0E TCRAB MSTP1 0 TMR_A TMR_B H FE10 TCRXY No conditi...

Page 540: ...TWR5 H FE26 TWR6 H FE27 TWR7 H FE28 TWR8 H FE29 TWR9 H FE2A TWR10 H FE2B TWR11 H FE2C TWR12 H FE2D TWR13 H FE2E TWR14 H FE2F TWR15 MSTP0 0 LPC H FE30 IDR3 H FE31 ODR3 H FE32 STR3 H FE34 LADR3H H FE35...

Page 541: ...H FE4A PEDDR write PFPIN read H FE4B PFDDR write H FE4C PCODR H FE4D PDODR No condition PORT PCPIN read H FE4E PCDDR write PDPIN read H FE4F PDDDR write H FED4 ICXR_0 H FED5 ICXR_1 No condition IIC_0...

Page 542: ...81 FLMCR2 H FF82 PCSR FLSHE 0 in STCR PWM EBR1 FLSHE 1 in STCR FLASH H FF83 SYSCR2 FLSHE 0 in STCR SYSTEM EBR2 FLSHE 1 in STCR FLASH H FF84 SBYCR FLSHE 0 in STCR SYSTEM H FF85 LPWRCR H FF86 MSTPCRH H...

Page 543: ...7 TOCR ICRAH ICRS 0 in TOCR H FF98 OCRARH MSTP13 0 ICRS 1 in TOCR FRT ICRAL ICRS 0 in TOCR H FF99 OCRARL ICRS 1 in TOCR ICRBH ICRS 0 in TOCR H FF9A OCRAFH ICRS 1 in TOCR ICRBL ICRS 0 in TOCR H FF9B OC...

Page 544: ...P3PCR H FFB0 P1DDR H FFB1 P2DDR H FFB2 P1DR H FFB3 P2DR H FFB4 P3DDR H FFB5 P4DDR H FFB6 P3DR H FFB7 P4DR H FFB8 P5DDR H FFB9 P6DDR H FFBA P5DR H FFBB P6DR H FFBC PBODR H FFBD P8DDR write PBPIN read H...

Page 545: ...D1 TCNT_1 H FFD3 PWOERA No condition PWM H FFD5 PWDPRA H FFD6 PWSL MSTP11 0 H FFD7 PWDR0 to PWDR7 H FFD8 ICCR_0 MSTP4 0 IICE 1 in STCR IIC_0 H FFD9 ICSR_0 H FFDE ICDR_0 ICE 1 in ICCR0 SARX_0 MSTP4 0 I...

Page 546: ...TMRX Y 0 in TCONRS TMR_X TCORA_Y MSTP8 0 HIE 0 in SYSCR TMRX Y 1 in TCONRS TMR_Y H FFF3 KMIMRA MSTP2 0 HIE 1 in SYSCR INT TICRF TMRX Y 0 in TCONRS TMR_X TCORB_Y MSTP8 0 HIE 0 in SYSCR TMRX Y 1 in TCON...

Page 547: ...port 7 Vin 0 3 to AVCC 0 3 V Reference supply voltage AVref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 4 3 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr 20 to...

Page 548: ...2 to IRQ0 3 IRQ5 to IRQ3 1 8 VT VT VCC 0 05 VCCB 0 05 V RES STBY NMI MD1 MD0 VCC 0 9 VCC 0 3 EXTAL VCC 0 7 VCC 0 3 Input high voltage PA7 to PA0 7 2 VIH VCCB 0 7 VCCB 0 3 V Port 7 VCC 0 7 AVCC 0 3 P97...

Page 549: ...multiplexed on that pin 4 P52 ExSCK1 SCL0 P97 SDA0 P86 SCK1 SCL1 P42 SDA1 and port G are NMOS push pull outputs When the SCL0 SDA0 SCL1 SDA1 ICE 1 ExSDAA ExSCLA ExSDAB or ExSCLB pin is used as an out...

Page 550: ...Vin 0 5 to VCC 0 5 V Vin 0 5 to VCC B 0 5 V Ports 1 to 3 5 150 Ports 6 and B to F 30 300 Input pull up MOS current Ports A 4 IP 30 600 A Vin 0 V VCC 3 0 V to 3 6 V VCC B 3 0 V to 5 5 V RES 80 pF NMI 4...

Page 551: ...istics depend on VCC B and the other pins characteristics depend on VCC 5 For flash memory programming erasure the applicable range is VCC 3 0 V to 3 6 V Table 22 2 DC Characteristics 3 When LPC Funct...

Page 552: ...L 1 mA Total of ports 1 2 and 3 40 Permissible output low current total Total of all output pins including the above IOL 60 mA Permissible output high current per pin All output pins IOH 2 mA Permissi...

Page 553: ...p Max Unit Test Conditions VT VCC 0 3 VCC 3 0 V to 3 6 V VT VCC 0 7 VCC 3 0 V to 3 6 V Schmitt trigger input voltage VT VT VCC 0 05 V VCC 3 0 V to 3 6 V Input high voltage VIH VCC 0 7 5 5 V VCC 3 0 V...

Page 554: ...selected Item Symbol Min Typ Max Unit Test Conditions 0 8 IOL 16 mA VCC B 4 5 V to 5 5 V 0 5 IOL 8 mA Output low voltage VOL 0 4 V IOL 3 mA 22 3 AC Characteristics Figure 22 3 shows the test condition...

Page 555: ...2 5 Clock Timing Condition VCC 3 0 V to 3 6 V VCC B 3 0 V to 5 5 V VSS 0 V 4 MHz to maximum operating frequency Ta 20 to 75 C Condition 10 MHz Item Symbol Min Max Unit Reference Clock cycle time tcyc...

Page 556: ...S 0 V 32 768 kHz 4 MHz to maximum operating frequency Ta 20 to 75 C Condition 10 MHz Item Symbol Min Max Unit Test Conditions RES setup time tRESS 300 ns RES pulse width tRESW 20 tcyc Figure 22 8 NMI...

Page 557: ...lay time tPWD 100 Input data setup time tPRS 50 I O ports Input data hold time tPRH 50 ns Figure 22 10 Timer output delay time tFTOD 100 Timer input setup time tFTIS 50 Figure 22 11 Timer clock input...

Page 558: ...RESO output pulse width tRESOW 132 tcyc Figure 22 20 Note Only peripheral modules that can be used in subclock operation Table 22 8 Keyboard Buffer Controller Timing Conditions VCC 3 0 V to 3 6 V VCC...

Page 559: ...time tSr 7 5 tcyc SCL SDA input fall time tSf 300 ns SCL SDA input spike pulse elimination time tSP 1 tcyc SDA input bus free time tBUF 5 tcyc Start condition input hold time tSTAH 3 tcyc Retransmiss...

Page 560: ...me tRXH 0 ns Figure 22 23 22 4 A D Conversion Characteristics Tables 22 11 list the A D conversion characteristics Table 22 11 A D Conversion Characteristics AN5 to AN0 Input 134 266 State Conversion...

Page 561: ...E 100 1200 ms block Reprogramming count NWEC 100 times Wait time after SWE bit setting 1 x 1 s Wait time after PSU bit setting 1 y 50 s z1 28 30 32 s 1 n 6 z2 198 200 202 s 7 n 1000 Wait time after P...

Page 562: ...t include the programming verification time 3 Block erase time Shows the total period for which the E bit in FLMCR1 is set It does not include the erase verification time 4 Maximum programming time tP...

Page 563: ...F Bypass capacitor Vcc power supply Vcc 3 0 V to 3 6 V Connect the Vcc power supply to the chip s VCL pin in the same way as the VCC pins It is recommended that a bypass capacitor be connected to the...

Page 564: ...00 05 04 page 530 of 544 tOSC1 tOSC1 EXTAL VCC STBY RES tDEXT tDEXT Figure 22 6 Oscillation Settling Timing NMI IRQi i 0 1 2 6 7 tOSC2 Figure 22 7 Oscillation Setting Timing Exiting Software Standby...

Page 565: ...l Timing The control signal timings are shown below tRESW tRESS tRESS RES Figure 22 8 Reset Input Timing tIRQS tNMIS tNMIH IRQi Edge input i 7 to 0 NMI tIRQS tIRQH IRQi i 7 to 0 IRQi Level input i 7 t...

Page 566: ...odule timings are shown below Ports 1 to 9 and A to G read T2 T1 tPWD tPRH tPRS Ports 1 to 6 8 9 and A to G write Figure 22 10 I O Port Input Output Timing tFTIS tFTOD FTOA FTOB FTIA FTIB FTIC FTID Fi...

Page 567: ...Bit Timer Output Timing TMCI0 TMCI1 TMIX TMIY ExTMIX ExTMIY TMIA TMIB tTMCS tTMCS tTMCWH tTMCWL Figure 22 14 8 Bit Timer Clock Input Timing tTMRS TMRI0 TMRI1 TMIX TMIY ExTMIX ExTMIY TMIA TMIB Figure 2...

Page 568: ...K Clock Input Timing TxD1 ExTxD1 transmit data RxD1 ExRxD1 receive data SCK1 ExSCK1 tRXS tRXH tTXD Figure 22 18 SCI Input Output Timing Synchronous Mode ADTRG tTRGS Figure 22 19 A D Converter External...

Page 569: ...medium speed mode KCLK PS2AC to PS2CC KD PS2AD to PS2CD Figure 22 21 Keyboard Buffer Controller Timing SDA0 SDA1 ExSDAA ExSDAB VIL VIH tBUF P P S tSTAH tSCLH tSr tSCLL tSCL tSf tSDAH Sr tSDAS tSTAS t...

Page 570: ...N Transmit signal LAD3 to LAD0 SERIRQ CLKRUN LFRAME Receive signal tTXD tRXH tRXS tOFF LAD3 to LAD0 SERIRQ CLKRUN Transmit signal tLcyc tLCKH LCLK tLCKL Figure 22 23 Host Interface LPC Timing Testing...

Page 571: ...t port Input port Port 8 T T kept kept kept kept I O port I O port Port 97 T T kept kept kept kept I O port I O port Port 96 EXCL T T DDR 1 H DDR 0 T EXCL input DDR 1 clock output DDR 0 T EXCL input E...

Page 572: ...ge 538 of 544 B Product Codes Product Type Product Code Mark Code Package Package Code H8S 2111B B HD64F2111BVB F2111BVTE10B H8S 2111B C Flash memory version 3 V version HD64F2111BVC F2111BVTE10C 144...

Page 573: ...ave priority Package Code JEDEC EIAJ Weight reference value TFP 144 Conforms 0 6 g Unit mm Dimension including the plating thickness Base material dimension 108 73 1 36 0 8 0 08 0 07 M 18 0 0 2 72 144...

Page 574: ...Rev 1 00 05 04 page 540 of 544...

Page 575: ...1 Clock pulse generator 455 Clocked synchronous mode 264 CMI 215 CMIA 215 CMIAAB 215 CMIAY 215 CMIB 215 CMIBAB 215 CMIBY 215 Compare match count mode 210 Condition field 39 Condition code register 24...

Page 576: ...215 OVIY 215 Parity error 256 Power down modes 463 Program counter 23 Program erase protection 450 Program program verify 446 Program counter relative 42 Programmer mode 452 Pulse output 169 PWM conve...

Page 577: ...R 122 486 494 502 510 PADDR 125 485 494 502 510 PAODR 125 485 494 502 510 PAPIN 126 485 494 502 510 PBDDR 129 486 494 502 510 PBODR 129 485 494 502 510 PBPIN 130 485 494 502 510 PCDDR 132 482 491 499...

Page 578: ...OCR 167 484 493 501 509 TSR 238 TWR 381 481 490 497 506 WSCR 94 486 494 502 510 WUEMRB 73 482 491 499 507 Reset 61 Reset exception handling 61 Resolution 149 ROM 431 Serial communication interface SCI...

Page 579: ...B Publication Date Rev 1 00 May 14 2004 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd...

Page 580: ...cher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688...

Page 581: ......

Page 582: ...H8S 2111B Hardware Manual...

Reviews:

No comments

Related manuals for H8S/2111B

Brand: D-Link Pages: 12

Brand: Hama Pages: 4

Brand: QSC Pages: 28

SCSI PC Card REX-9530V

Brand: Ratoc Systems Pages: 30

Brand: SMART Pages: 15

EXPANSION CARD X-DANTE

Brand: Behringer Pages: 65

Brand: Alesis Pages: 61

PowerBeam AC Gen2

Brand: Ubiquiti Pages: 22

Brand: Idis Pages: 31

Marconi OMS 1200

Brand: Ericsson Pages: 136

Optane Persistent Memory 200 Series

Brand: Supermicro Pages: 54

Brand: Freescale Semiconductor Pages: 8

NVRx-7300 series

Brand: Swann Pages: 9

PG-Flex FLC-704

Brand: PairGain Pages: 20

PowerMatch ESPLink

Brand: Bose Pages: 2

J-Link-OB-STM32F072-128KB

Brand: Segger Pages: 18

CHEETAH ST34501FC

Brand: Seagate Pages: 68

Brand: Accusys Pages: 34

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands