Renesas H8S/2111B, Hardware Manual

Page: 101 / 582

Rev. 1.00, 05/04, page 67 of 544
Section 5 Interrupt Controller
5.1 Features
•
Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
•
Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI and address break.
•
Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
•
Thirty-one external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for
IRQ7
to
IRQ0
. The IRQ6 interrupt is shared by the interrupt from
the
IRQ6
pin and eight external interrupt inputs (
KIN7
to
KIN0
), and the IRQ7 interrupt is
shared by the interrupt from the
IRQ7
pin and sixteen external interrupt inputs (
KIN15
to
KIN8
and
WUE7
to
WUE0
).
KIN15
to
KIN0
and
WUE7
to
WUE0
can be masked
individually by the user program.