Renesas H8S/2111B, Hardware Manual

Page: 445 / 582

Rev. 1.00, 05/04, page 411 of 544
15.6 Usage Notes
15.6.1 Module Stop Mode Setting
LPC operation can be enabled or disabled using the module stop control register. The initial
setting is for LPC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 20, Power-Down Modes.
15.6.2 Notes on Using Host Interface
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid
data contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
Table 15.9 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15 when LADR3 = H'A24F and LADR3 = H'3FD0.