Renesas H8S/2111B, Hardware Manual

Page: 372 / 582

Rev. 1.00, 05/04, page 338 of 544
5. The I
2
C bus interface specification for the SCL rise time t
sr
is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 13.9.
Table 13.9 Permissible SCL Rise Time (t
sr
) Values
Time Indication
[ns]
IICX t
cyc
Indication
I
2
C Bus
Specification
(Max.)
φ
=
5 MHz
φ
=
8 MHz
φ
=
10 MHz
Standard mode 1000 1000 937 750 0 7.5 t
cyc
High-speed mode 300 300 300 300
Standard mode 1000 1000 1000 1000 1 17.5 t
cyc
High-speed mode 300 300 300 300
6. The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
cyc
, as shown in
table 13.8. However, because of the rise and fall times, the I
2
C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 13.10 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.
t
SCLLO
in high-speed mode and t
STASO
in standard mode fail to satisfy the I
2
C bus interface
specifications for worst-case calculations of t
Sr
/t
Sf
. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
2
C bus.