Renesas H8S/2111B, Hardware Manual

Page: 500 / 582

Rev. 1.00, 05/04, page 466 of 544
Bit Bit Name
Initial
Value R/W Description
6 LSON 0 R/W Low-Speed On Flag
Specifies the operating mode to be entered after
executing the SLEEP instruction. This bit also controls
whether to shift to high-speed mode or subactive mode
when watch mode is cancelled.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or
watch mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (
φ
SUB)
input from the EXCL pin is sampled using the clock (
φ
)
generated by the system clock pulse generator. Clear
this bit to 0 when
φ
is 5 MHz or more.
0: Sampling using
φ
/32 clock
1: Sampling using
φ
/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3

0 R/W Reserved
An undefined value is read from this bit. This bit should
not be set to 1.
2 to 0

All 0 R Reserved
These bits are always read as 0 and cannot be
modified.