Renesas 7700 FAMILY, User Manual

Page: 288 / 540

CONNECTION WITH EXTERNAL DEVICES
7751 Group User’s Manual
12–23
12.4 Hold function
Fig. 12.4.4 Timing of acceptance of Hold request and termination of Hold state (3)
Address B
E
ALE
HLDA
HOLD
R/W
External address bus
BHE
<When inputting “L” level to
HOLD
pin during term using bus; when data access is
completed with continuous 2-bus cycle>
16
8
16
(Access from odd address)
Using
●
State when inputting “L” level to
HOLD
pin
External data bus Data length External data bus width
Judgment timing of input
level to HOLD pin
Clock
1
External address bus
/
External data bus
Address A+1
➀
1
✕
1
Not accepted
Address A
Data Data
Floating
Floating
Floating
Hold state
Term using bus
Term using bus
➁
➀
When accepting a Hold request, not a new address but an
address output just before is output again.
➁
Hold request cannot be accepted before input/output of 16-bit
data is completed.
Notes 1: This figure shows the case of 2 access in low-speed running.
2: Clock
1
has the same polarity and the same frequency as
BIU
.
Signals timing to be input or output externally is ordained by clock
1
as a basis.
3: This term indicated by Note 3 becomes 1.5 cycles in 5 access in high-speed
running. It is because the level judgment timing becomes the 1.5 cycles before the
end of the term using bus (See Table 12.4.2.)
✽
(Note 3)
1
✕
1