Renesas 7700 FAMILY, User Manual

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CENTRAL PROCESSING UNIT (CPU)
7751 Group User’s Manual
2–23
2.5.1 Single-chip mode
Use this mode when not using external devices. In this mode, ports P0 to P8 function as programmable
I/O ports (when using an internal peripheral device, they function as its I/O pins).
In the single-chip mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.
2.5.2 Memory expansion and microprocessor modes
Use these modes when connecting devices externally. In these modes, an external device can be connected
to any required location in the 16-Mbyte access space. For access to external devices, refer to “Chapter
12. CONNECTION WITH EXTERNAL DEVICES.”
The memory expansion and microprocessor modes have the same functions except for the following:
•In the microprocessor mode, access to the internal ROM area is disabled by force, and the internal ROM
area is handled as an external area.
•In the microprocessor mode, port P4
2
always functions as the clock
φ
1
output pin.
In the memory expansion and microprocessor modes, P0 to P3, P4
0
, and P4
1
function as the I/O pins for
the signals required for accessing external devices. Consequently, these pins cannot be used as programmable
I/O ports.
If an external device is connected with an area with which the internal area overlaps, when this overlapping
area is read, data in the internal area is taken in the CPU, but data in the external area is not taken in.
If data is written to an overlapping area, the data is written to the internal area, and a signal is output
externally at the same timing as writing to the internal area.
Figure 2.5.2 shows a pin configuration in each processor mode. Table 2.5.1 lists the functions of P0 to P4
in each processor mode.
For the function of each pin, refer to section “1.3 Pin description,” “Chapter 3. INPUT/OUTPUT PINS,”
and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
2.5 Processor modes