Renesas 7700 FAMILY, User Manual

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CONNECTION WITH EXTERNAL DEVICES
7751 Group User's Manual 12–13
12.2 Bus cycle
Table 12.2.2 Bus cycle
1 bus cycle = 2
2 access in
high-speed running
(RAM)
1 bus cycle = 3
3 access in high-speed
1 bus cycle = 4
4 access in high-speed running
2 access in
low-speed running
1 bus cycle = 2
2 access in
low-speed running
1 bus cycle = 2
3 access in
low-speed running
1 bus cycle = 3
4 access in
low-speed running
1 bus cycle = 4
5 access in high-speed running
1 bus cycle = 5
1 bus cycle = 3
3 access in high-speed
running (ROM, SFR)
ALE
Reading
Writing
Note : Signals when accessing an internal area means signals which are output from pins
externally when accessing an internal area in the memory expansion mode.
A: Address W: Data to be written
R: Data to be read ?: Undefined value
E
High-speed running [ f (X
IN
)
≤
40 MHz ]
Low-speed running [ f (X
IN
)
≤
25 MHz ]
Internal area access External area access Internal area access External area access
(Note)
(Note)
A
A W
Reading
Writing
A
A W
R
ALE
E
Reading
Writing
A
A W
R
ALE
E
Reading
Writing
A
W
R
E
A
Reading
Writing
A
?
ALE
E
A
Writing
W
ALE
E
A
A
Reading
Writing
W
ALE
E
A
A
Reading
R
Writing
W
ALE
E
A
Reading
R A
Writing
W
ALE
E
A
Reading
R A
Writing
W A
Reading R A
Writing
W
ALE
E
A
Reading R A
running