Renesas 7700 FAMILY, User Manual

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CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
7751 Group User’s Manual
12–6
(2) External data bus width switching signal (BYTE pin level)
This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal
level is “L,” the external data bus width is 16 bits; when the level is “H,” the bus width is 8 bits (refer
to Table 12.1.1.)
Fix this signal to either “H” or “L” level.
This signal is valid only for the external areas. When accessing the internal areas, the data bus width
is always 16 bits.
(3)
__
Enable signal (E)
This signal becomes “L” level while reading or writing data to and from the data bus. (See Table
12.1.2.)
(4)
__
Read/Write signal (R/W)
This signal indicates the state of the data bus. This signal becomes “L” level while writing to the data
_ __
bus. Table 12.1.2 lists the state of the data bus indicated with the E and R/W signals.
_
Table 12.1.2 State of data bus indicated with E
__
and R/W signals
__
R/W
H
L
H
L
_
E
H
L
State of data bus
Not used
Read data
Write data
(5)
____
Byte high enable signal (BHE)
This signal indicates the access to an odd address. This signal becomes “L” level when accessing
an only odd address or when simultaneously accessing odd and even addresses.
This signal is used to connect memories or I/O devices of which data bus width is 8 bits when the
external data bus width is 16 bits.
____
Table 12.1.3 lists levels of the external address bus A
0
and the
BHE
signal and access addresses.
____
Table 12.1.3 Levels of A
0
and BHE signal and access addresses
Access address
A
0
____
BHE
Even and odd addresses
(Simultaneous 2-byte access)
L
L
Even address
(1-byte access)
L
H
Odd address
(1-byte access)
H
L
(6) Address latch enable signal (ALE)
This signal is used to obtain the address from the multiplexed signal of address and data that is input
and output to and from the A
8
/D
8
to A
15
/D
15
and A
16
/D
0
to A
23
/D
7
pins. Make sure that when this signal
is “H,” latch the address and simultaneously output the addresses. When this signal is “L,” retain the
latched address.
(7)
____
Ready function-related signal (
RDY
)
This is the signal to use the Ready function. (Refer to section “12.3 Ready function.”)
(8)
_____ _____
Hold function-related signals (
HOLD
,
HLDA
)
These are the signals to use the Hold function. (Refer to section “12.4 Hold function.”)