Renesas 7700 FAMILY, User Manual

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CLOCK GENERATING CIRCUIT
14–5
7751 Group User’s Manual
14.2.2 Operation clock for internal peripheral devices
The operation clock for the internal peripheral devices uses
φ
or
φ
divided by 2 as its clock source.
The clock source of the operation clock for internal peripheral devices is selected by the clock source for
peripheral devices select bit (bit 2 at address 5F
16
).
Figure 14.2.2 shows the structure of processor mode register 1 (address 5F
16
).
When f(X
IN
) > 25 MHz, fix the clock source for peripheral devices select bit to “0.”
14.2 Clock
b7 b6 b5 b4 b3 b2 b1 b0
Processor mode register 1 (Address 5F
16
)
Bit
5
Bus cycle select bits
3
2
1, 0
Bit name
At reset
0
RW
Functions
In high-speed running
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
Note: Fix this bit to “0” when f(X
IN
) > 25 MHz.
Fix these bits to “0.”
4
7, 6
RW
RW
RW
RW
0
0
0
Clock source for peripheral
devices select bit
(Note)
0 : divided by 2
1 :
CPU running speed select bit
(Note)
0 : High-speed running
1 : Low-speed running
RW
0
RW
0
b5 b4
In low-speed running
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
b5 b4
Fix these bits to “0.”
0 0 0 0
: Bits 0, 1, and bits 3 to 7 are not used for the clock generating circuit.
Fig. 14.2.2 Structure of processor mode register 1