Renesas 7700 FAMILY, User Manual

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7751 Group User’s Manual
2.1 Central processing unit
CENTRAL PROCESSING UNIT (CPU)
2–5
2.1.5 Program counter (PC)
The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at
which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. The contents of the high-order program counter (PC
H
) become “FF
16
,” and the
low-order program counter (PC
L
) becomes “FE
16
” at reset. The contents of the program counter becomes
the contents of the reset’s vector address (addresses FFFE
16
, FFFF
16
) immediately after reset.
Figure 2.1.3 shows the program counter and the program bank register.
Fig. 2.1.3 Program counter and program bank register
2.1.6 Program bank register (PG)
The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the
address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out
from an instruction queue buffer next) is stored. These 8 bits are called bank.
When a carry occurs after adding the contents of the program counter or adding the offset value to the
contents of the program counter in the branch instruction and others, the contents of the program bank
register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the
program counter, the contents of the program bank register is automatically decremented by 1. Accordingly,
there is no need to consider bank boundaries in programming, usually.
In the single-chip mode, make sure to prevent the program bank register from being set to the value other
than “00
16
” by executing the branch instructions and others. It is because the access space of the single-
chip mode is the internal area within the bank 0
16
.
This register is cleared to “00
16
” at reset.
PC
H
PC
L
b7 b0 b15 b8 b7 b0
(b16) (b23)
PG