Renesas 7700 FAMILY, User Manual

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APPLICATIONS
7751 Group User’s Manual 17–4
17.1 Memory expansion
17.1.2 How to calculate timing
When expanding a memory, use a memory of which standard specifications satisfy the address access
time and the data setup time for write. The following describes how to calculate each timing.
➀
External memory’s address access time; t
a(AD)
t
a(AD)
= t
su(P0A/P1A/P2A-P1D/P2D)
– (address decode time
✽
1 + address latch delay time
✽
2 )
Address decode time
✽
1
: Time required for the chip select signal to be enabled after decoding address
Address latch delay time
✽
2 : Delay time required when latching address (Unnecessary in minimum model)
➁
External memory’s data setup time for write; t
su(D)
t
su(D)
= t
w(EL)
– t
d(E–P2Q/P1Q)
t
d(E–P2Q/P1Q)
: t
d(E–P2Q)
or t
d(E–P1Q)
Table 17.1.2 lists the data or the calculation formulas for each parameter. Figure 17.1.1 shows the bus
timing diagram. Figures 17.1.2 and 17.1.4 show the relationship between t
su(P0A/P1A/P2A-P1D/P2D)
and f(X
IN
);
Figures 17.1.3 and 17.1.5 show the relationship between t
su(D)
and f(X
IN
).
Table 17.1.2 Data or calculation formulas for each parameter (unit: ns)
Parameter
Bus cycle
Low-speed running
2
φ
access
Low-speed running
3
φ
access
Low-speed running
4
φ
access
High-speed running
3
φ
access
High-speed running
4
φ
access
High-speed running
5
φ
access
– 65
3
✕
10 9
f(X
IN
)
t
su(P0A/P1A/P2A
—P1D/P2D)
t
w(EL)
t
d(E-P2Q)
t
d(E-P1Q)
– 65
5
✕
10 9
f(X
IN
)
– 65
7
✕
10
9
f(X
IN
)
– 75
5
✕
10
9
f(X
IN
)
– 75
7
✕
10 9
f(X
IN
)
– 75
9
✕
10
9
f(X
IN
)
– 25
4
✕
10 9
f(X
IN
)
– 25
3
✕
10 9
f(X
IN
)
– 25
– 25
4
✕
10
9
f(X
IN
)
– 25
4
✕
10
9
f(X
IN
)
6
✕
10 9
f(X
IN
)
– 25
2
✕
10
9
f(X
IN
)
35
35 35 35 35
35