Renesas 7700 FAMILY, User Manual

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SERIAL I/O
7751 Group User’s Manual
7–12
The UARTi receive register is used to convert serial data which is input to the RxD
i
pin into parallel data.
This register takes in the input signal to the RxD
i
pin synchronously with the transfer clock, one bit at a
time.
The UARTi receive buffer register is used to read out receive data. When reception is completed, receive
data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer
register. The contents of UARTi receive buffer register is updated when the next data is ready before
reading out the data which has been transferred to the UARTi receive buffer register (i.e., an overrun error
occurs).
When selecting the “MSB first” in the clock synchronous serial I/O mode, bit position of data in the UARTi
receive buffer register is reversed, and then the data of which bit position was reversed is read out, as
receive data. (Refer to section “7.3.2 Transfer data format.”) Reception operation itself is the same
whichever format is selected, “LSB first” or “MSB first.”
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35
16
,
3D
16
) to “1” after clearing it to “0.”
Figure 7.2.9 shows the contents of UARTi receive buffer register when reception is completed.
7.2 Block description
Fig. 7.2.9 Contents of UARTi receive buffer register when reception is completed
b7 b0 b7 b0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
Receive data (9 bits)
Receive data (8 bits)
Receive data (7 bits)
In UART mode
(Transfer data length : 9 bits)
In clock synchronous
serial I/O mode
In UART mode
(Transfer data length : 8 bits)
In UART mode
(Transfer data length : 7 bits)
Same value as bit
7 in low-order byte
Same value as bit
6 in low-order byte
High-order byte
(addresses 37
16
, 3F
16
)
Low-order byte
(addresses 36
16
, 3E
16
)