Renesas 7700 FAMILY, User Manual

Page: 471 / 540

APPENDIX
Appendix 3. Control registers
7751 Group User’s Manual 20–20
Timer Mode
b7 b0 b7 b0
(b15) (b8)
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A1 register (Addresses 49
16
, 48
16
)
Timer A2 register (Addresses 4B
16
, 4A
16
)
Timer A3 register (Addresses 4D
16
, 4C
16
)
Timer A4 register (Addresses 4F
16
, 4E
16
)
Functions Bit
At reset
RW
15 to 0 These bits can be set to “0000
16
” to “FFFF
16
.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
Undefined
RW
Gate function select bits
Pulse output function select bit
1
Operating mode select bits
Bit name Functions
b7 b6 b5 b4 b3 b2 b1 b0
Timer Ai mode register (i = 0 to 4) (Addresses 56
16
to 5A
16
)
0 0 : Timer mode
0 : No pulse output
(TAi
OUT
pin functions as a programmable
I/O port.)
1 : Pulse output
(TAi
OUT
pin functions as a pulse output
pin.)
0 0 : f
2
/ f
4
0 1 : f
16
/ f
32
1 0 : f
64
/ f
128
1 1 : f
512
/ f
1024
b7 b6
Count source select bits
b1 b0
b4 b3
0 0
0 0 : No gate function
0 1 : (TAi
IN
pin functions as a prog-
rammable I/O port.)
1 0 : Counter counts only while TAi
IN
pin’s input signal is “L” level.
1 1 : Counter counts only while TAi
IN
pin’s input signal is “H” level.
Bit
4
At reset
RW
0
2
0 RW
0 RW
0 RW
3
0 RW
0
RW
5
0 RW
6
7
0 RW
0 RW
0
Fix this bit to “0” in the timer mode.