Philips DVDR725H Service Manual Download Page 169

Page: 169 / 211

Circuit-, IC descriptions and list of abbreviations

EN 169

HDRW720/0x, DVDR725H/0x

9.8

EPG Europe Board

9.8.1

General

The ARM7 based microprocessor (item U1) and an ASIC
(Gemstar GSA03, item U2) generates the EPG OSD data
(RGB or YUV-interl./progr.). The host P on the Digital board,
controls both ICs via the I2C bus. A RAM memory (item U7)

and two Flash memories (items U8 and U9) with the firmware
and EPG data, belong also to the periphery of the ASIC.
A resistor and capacitor (items R1 and C6) generate the reset
for this system. The IPOR reset comes from the set and is
active after main power 'on'. A port expander from the host,
controls the nGCLR reset signal. This port expander (item U31)
is also used for switching the video paths on the EPG board.

Figure 9-9

Either the board works in 'Loop Trough' mode, or (for EPG) the
output path is switched to the 'EPG RGB' video.

9.8.2

Loop Trough

For 'Loop Trough', the input video signals (CVBS, YC, RGB,
YUV-interlaced, and YUV-progressive) from the digital board
are passing three video switches before going to the Analogue
board.
•

Item U15 for CVBS and Y/C selection between EPG and
Loop trough.

•

Items U16, U18, and U19 (and periphery) for RGB
selection between EPG and Loop trough.

•

Items U42 and U17 for YUV-interlaced and YUV-
progressive selection between EPG and Loop trough.
These signals are amplified (items U13B, C, and D) for
driving a 75-Ohm output.

Note: RGB and YUV-interlaced (VR_DVD, UB_DVD,
YG_DVD) are the same signals. It depends on the software,
which signal is chosen.

9.8.3

EPG RGB

A V-sync and H-sync (for progressive = 2H-sync) are
necessary for outputting an EPG video. A sync separator (item
U10) generates these syncs. Input for the sync separator is
either the 1fh or the 2fh luminance signal from the Digital board.
A video switch (item U50) makes the selection.

The EPG signal goes via a PIP-inserter IC (item U11 and
pheripherals) that inserts a PIP (Picture In Picture) into the
EPG OSD. Source for this PIP is the CVBS signal from the
digital board.
When the PIP output is a YUV signal, the Y signal is without a
sync. Therefore, this sync must is added with item U13A.

For RGB-to-CVBS, Y/C conversion is realized by a PAL
conversion IC (item U14). The oscillator (item Y5) is necessary
for generating the chroma carrier.

For scanning EPG data, the A_YCVBS signal from the Analog
board is used. This signal is fed to pin 189 of item U2.
There is also a sync from the Analog board necessary. A
discrete circuit (items Q18-Q23 and periphery) generates it.

9.8.4

Power supply

The supply for the video stages and the EPG digital part are
generated via DC-DC converters and linear regulators (items
U28, U40, and U41) out of the 12VSTBY.

9.9

I/O Extension Board

This board feeds the internal S/PDIF signal from the Digital
board to an optical and/or digital out connector. For European
players, also an YUV output is present on this board.

Digital

Board

Samsung

CPU

S3C3410x

NOR Flash

1M x 16

SDRAM

512k x 16 x 2Banks

Gemstar ASIC

GSA03

Discrete