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Summary of Contents for CEM2100/00

Page 1: ... 2 ISO PCB COMPONENTLAYOUT CD CONNECTOR PCB COMPONENT LAYOUT 20 19 15 16 13 14 11 12 MAIN PCB COMPONENT LAYOUT TUNER PCB COMPONENT LAYOUT 17 18 SD PCB COMPONENT REMOTE PCB COMPONENT LAYOUT 21 CEM2100 00 98 2011 6 29 DIAGRAM P Service Manual RECORDABLE REWRITABLE Mini System Service Service Version1 1 TABLE OF CONTENTS CIRCUIT ANEL CIRCUIT PANEL PCB COMPONENT LAYOUT LAYOUT 7 9 ...

Page 2: ...2 ...

Page 3: ...BLOCK DIAGRAM ...

Page 4: ...WIRING DIAGRAM 4 ...

Page 5: ...CIRCUIT DIAGRAM MAIN BOARD 5 ...

Page 6: ...6 ...

Page 7: ......

Page 8: ...4 330 R915 470 R916 680 R917 1K R920 3K3 R912 180 R924 NC R925 NC R922 82K R923 47K R930 22 R929 22 R928 22 R927 22 R926 10 LED901 BLUE R932 270 R933 270 R934 270 R935 270 R936 270 R937 270 R938 270 R939 270 R940 270 R941 270 R942 270 R943 270 R944 270 R945 270 R946 270 R947 270 LED902 BLUE LED903 BLUE LED904 BLUE LED905 BLUE LED906 BLUE LED907 BLUE LED908 BLUE LED909 BLUE LED910 BLUE LED911 BLUE ...

Page 9: ... VDD OSCO OSCI P10 P17 GND REM C3 1UF 25V 0805 BAT 3V VOL 5A EQ 10 VOL 83 POWER MUTE 59 DOWN 58 UP 82 PREV 5B SOURCE 0C NEXT 5C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IC1 1626 LED1 LD XT1 3 64MHz C2 22P C1 22P CIRCUIT DIAGRAM REMOTE BOARD ...

Page 10: ... 4K7 R003 47 XT001 32 768KHz C009 22P C112 103 C020 104 13 12 11 10 9 8 7 6 5 4 3 2 1 DATA CLK RES R OUT L OUT AM LOC AM IN AM AGC RFGND RFGND FM ANT 16 15 14 DGND A VCC D VCC DGND RDS CN001 TUNER23 C015 104 L007 220UH C013 333 C019 474 L004 FB152 Q004 9014S Q102 Q003 9014S Q002 9018S R006 220K R005 10M C017 183 L006 33UH L005 1MH C014 122 R004 10K R007 4K7 R008 4K7 C016 474 R010 10 C021 1U C020 1...

Page 11: ...PCB LAYOUT MAIN BOARD TOP SIDE VIEW 11 ...

Page 12: ...PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW 12 ...

Page 13: ...PCB LAYOUT PANEL BOARD TOP SIDE VIEW ...

Page 14: ...14 PCB LAYOUT PANEL BOARD BOTTOM SIDE VIEW ...

Page 15: ...PCB LAYOUT REMOTE BOARD TOP SIDE VIEW 15 ...

Page 16: ...PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW 16 ...

Page 17: ...PCB LAYOUT TUNER BOARD TOP SIDE VIEW 17 ...

Page 18: ...PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 18 ...

Page 19: ...PCB LAYOUT SD BOARD TOP SIDE VIEW ...

Page 20: ...20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW ...

Page 21: ...PCB LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 ...

Page 22: ...22 SET EXPLODER VIEW DRAWING ...

Page 23: ...1 of 2 CEM2100 Trouble shooting Trouble shooting Trouble shooting Trouble shooting ...

Page 24: ...k the circuit of power amplifier IC501 LV47004 and VOL IC403 PT7313E 3 f To check the oscillation frequence of crystal X201 shuold be 8MHz and for the crystal X202 should be 32 768KHZ b To check whether the unit is at MUTE mode press SOURCE button and check whether it is effective of the input sound source c To check whether the connection of 8PIN audio output wire of ISO connector is correct wron...

Page 25: ...t failure cause failure phenomena remark CD defective l To check the voltage of the 8 pin of IC 603 should be 8V m To check whether the rotation belt of deck mechanism is dislocation or loose 5 b To check whether there is any abnormal of the rotation of the deck mecahnism or whether the disc is enter in position h To check the oscillation frequence of crystal X603 should be 9MHZ j To check the swi...

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Page 91: ...bá íbá å ëEñNæaÞ ß Þ ç æ î ë_ä ß ÝaÞ ï ð Ú ÝEáGàKà ß ë âNä ÜáòæKß ÜàKá æ Þ æ ßGà Ûcß æ ð î Ý á àKà ß ëEâ ä Üá4ê îÞ å Û Þ çGå ë ß Ü Ü á ä ÝEáGàNà ß ëEâGæ á ä ð î å Û Þ çGå ë ë ñ ïDã ç Þ ß âGâ á ëEÛ àKá å Û ð Ú Ú Ú Ý á àKà ß ëEâ ß ä Þ Û åWå ÛGß â ëEñ äGëÌæGì Û â ê ëEâ ð Ú ÝEáGàNà ß ëEâÂÜ ÜKæ æGç Û6å ÛGæGç à_Û è Üß é äÌå ÛGæGç à_Û Ý ì Û ÝEíQá íQáGå ßGç Þ á è Üß éQä å á àRä å æ Þ æ á ëEñÙäÌå Û æGç à_Û...

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Page 111: ...8 Bit Microcontroller TLCS 870 C Series T5CL8 ...

Page 112: ...or usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may cause loss of human life or bodily injury Unintended Usage Unintended Usage include atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments medical instruments all types of safet...

Page 113: ...Revision History Date Revision 2008 7 31 1 First Release ...

Page 114: ......

Page 115: ... mode 2 2 3 3 STOP mode 2 2 4 Operating Mode Control 18 2 2 4 1 STOP mode 2 2 4 2 IDLE1 2 mode and SLEEP1 2 mode 2 2 4 3 IDLE0 and SLEEP0 modes IDLE0 SLEEP0 2 2 4 4 SLOW mode 2 3 Reset Circuit 31 2 3 1 External Reset Input 31 2 3 2 Address trap reset 32 2 3 3 Watchdog timer reset 32 2 3 4 System clock reset 32 3 Interrupt Control Circuit 3 1 Interrupt latches IL23 to IL2 35 3 2 Interrupt enable re...

Page 116: ...rent Port 58 5 7 Port P6 P67 to P60 59 5 8 Port P7 P77 to P70 62 6 Watchdog Timer WDT 6 1 Watchdog Timer Configuration 65 6 2 Watchdog Timer Control 66 6 2 1 Malfunction Detection Methods Using the Watchdog Timer 66 6 2 2 Watchdog Timer Enable 67 6 2 3 Watchdog Timer Disable 68 6 2 4 Watchdog Timer Interrupt INTWDT 68 6 2 5 Watchdog Timer Reset 69 6 3 Address Trap 70 6 3 1 Selection of Address Tra...

Page 117: ...and 4 111 10 3 6 16 Bit Event Counter Mode TC3 and 4 112 10 3 7 16 Bit Pulse Width Modulation PWM Output Mode TC3 and 4 112 10 3 8 16 Bit Programmable Pulse Generate PPG Output Mode TC3 and 4 115 10 3 9 Warm Up Counter Mode 117 10 3 9 1 Low Frequency Warm up Counter Mode NORMAL1 NORMAL2 SLOW2 SLOW1 10 3 9 2 High Frequency Warm Up Counter Mode SLOW1 SLOW2 NORMAL2 NORMAL1 11 8 Bit TimerCounter TC5 T...

Page 118: ...ffer Empty 146 12 9 6 Transmit End Flag 147 13 Asynchronous Serial interface UART2 13 1 Configuration 149 13 2 Control 150 13 3 Transfer Data Format 152 13 4 Transfer Rate 153 13 5 Data Sampling Method 153 13 6 STOP Bit Length 154 13 7 Parity 154 13 8 Transmit Receive Operation 154 13 8 1 Data Transmit Operation 154 13 8 2 Data Receive Operation 154 13 9 Status Flag 155 13 9 1 Parity Error 155 13 ...

Page 119: ...Acknowledgment mode ACK 1 16 5 1 2 Non acknowledgment mode ACK 0 16 5 2 Number of transfer bits 200 16 5 3 Serial clock 200 16 5 3 1 Clock source 16 5 3 2 Clock synchronization 16 5 4 Slave address and address recognition mode specification 201 16 5 5 Master slave selection 201 16 5 6 Transmitter receiver selection 201 16 5 7 Start stop condition generation 202 16 5 8 Interrupt service request and...

Page 120: ...6 19 2 4 Product ID Entry 226 19 2 5 Product ID Exit 226 19 2 6 Security Program 226 19 3 Toggle Bit D6 227 19 4 Access to the Flash Memory Area 228 19 4 1 Flash Memory Control in the Serial PROM Mode 228 19 4 1 1 How to write to the flash memory by executing the control program in the RAM area in the RAM loader mode within the serial PROM mode 19 4 2 Flash Memory Control in the MCU mode 230 19 4 ...

Page 121: ...atus Code 258 20 13 Specifying the Erasure Area 260 20 14 Flowchart 261 20 15 UART Timing 262 21 Input Output Circuit 21 1 Control pins 263 21 2 Input Output Ports 264 22 Electrical Characteristics 22 1 Absolute Maximum Ratings 267 22 2 Operating Conditions 268 22 2 1 MCU mode Flash Programming or erasing 268 22 2 2 MCU mode Except Flash Programming or erasing 268 22 2 3 Serial PROM mode 269 22 3 ...

Page 122: ...viii ...

Page 123: ...IBA products listed in this document shall be made at the customer s own risk 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture use and or sale are prohibited under any applicable laws and regulations 060106_Q The information contained herein is presented only as a guide for the applications of our products No responsibil...

Page 124: ...IDLE0 mode CPU stops and only the Time Based Timer TBT on peripherals operate using high fre quency clock Release by falling edge of the source clock which is set by TBTCR TBTCK IDLE1 mode CPU stops and peripherals operate using high frequency clock Release by interru puts CPU restarts IDLE2 mode CPU stops and peripherals operate using high and low frequency clock Release by inter ruputs CPU resta...

Page 125: ...8 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P65 AIN5 STOP1 P67 AIN7 STOP3 P70 AIN8 P72 AIN10 P71 AIN9 P74 AIN12 P73 AIN11 P66 AIN6 STOP2 P14 TC4 PDO4 PWM4 PPG4 P13 TC3 PDO3 PWM3 P12 PPG P11 DVO P10 TC1 P47 P46 SCK2 P45 SO2 BOOT RXD1 P01 XIN P07 INT2 AVDD P60 AIN0 P61 AIN1 P64 AIN4 STOP0 P62 AIN2 VAREF P63 AIN3 P44 SI2 P43 P42 TXD2 P41 RXD2 P40 P77 AIN15 P76 AIN14 P75 AIN13 INT3 TC2 P15 PD...

Page 126: ...Page 4 1 3 Block Diagram T5CL8 1 3 Block Diagram Figure 1 2 Block Diagram ...

Page 127: ...T data output 1 P01 RXD1 BOOT 11 IO I I PORT01 UART data input 1 Serial PROM mode control input P00 INT0 10 IO I PORT00 External interrupt 0 input P17 TC6 PDO6 PWM6 PPG6 51 IO I O PORT17 TC6 input PDO6 PWM6 PPG6 output P16 TC5 PDO5 PWM5 50 IO I O PORT16 TC5 input PDO5 PWM5 output P15 TC2 INT3 49 IO I I PORT15 TC2 input External interrupt 3 input P14 TC4 PDO4 PWM4 PPG4 48 IO I O PORT14 TC4 input PD...

Page 128: ... IO I PORT44 Serial data input 2 P43 39 IO PORT43 P42 TXD2 38 IO O PORT42 UART data output 2 P41 RXD2 37 IO I PORT41 UART data input 2 P40 36 IO PORT40 P54 56 IO PORT54 P53 55 IO PORT53 P52 54 IO PORT52 P51 SDA 53 IO IO PORT51 I2C bus data P50 SCL 52 IO IO PORT50 I2C bus clock P67 AIN7 STOP3 27 IO I I PORT67 Analog Input7 STOP3 input P66 AIN6 STOP2 26 IO I I PORT66 Analog Input6 STOP2 input P65 AI...

Page 129: ...O I PORT73 Analog Input11 P72 AIN10 30 IO I PORT72 Analog Input10 P71 AIN9 29 IO I PORT71 Analog Input9 P70 AIN8 28 IO I PORT70 Analog Input8 XIN 2 I Resonator connecting pins for high frequency clock XOUT 3 O Resonator connecting pins for high frequency clock RESET 8 I Reset signal TEST 4 I Test pin for out going test Normally be fixed to low VAREF 18 I Analog Base Voltage Input Pin for A D Conve...

Page 130: ...Page 8 1 4 Pin Names and Functions T5CL8 ...

Page 131: ...ta Memory RAM The T5CL8 has 2048 bytes Address 0040H to 083FH of internal RAM The first 192 bytes 0040H to 00FFH of the internal RAM are located in the direct area instructions with shorten operations are available against such an area SFR 0000H 64 bytes SFR RAM Special function register includes I O ports Peripheral control registers Peripheral status registers System control registers Program st...

Page 132: ...sumption can be reduced by switching of the standby controller to low power operation based on the low frequency clock The high frequency fc clock and low frequency fs clock can easily be obtained by connecting a resonator between the XIN XOUT and XTIN XTOUT pins respectively Clock input from an external oscillator is also possible In this case external clock is applied to XIN XTIN pin with XOUT X...

Page 133: ...illation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program The system to require the adjustment of the oscillation frequency should create the program for the adjust ment in advance XOUT XIN Open XOUT XIN XTOUT XTIN Open XTOUT XTIN a Crystal Ceramic resonator b External oscillator c Crystal d External oscillator High frequency clock...

Page 134: ...ration of timing generator The timing generator consists of a 2 stage prescaler a 21 stage divider a main system clock generator and machine cycle counters An input clock to the 7th stage of the divider depends on the operating mode SYSCR2 SYSCK and TBTCR DV7CK that is shown in Figure 2 4 As reset and STOP mode started canceled the prescaler and the divider are cleared to 0 Figure 2 4 Configuratio...

Page 135: ... 4 states S0 to S3 and each state consists of one main system clock Figure 2 5 Machine Cycle 2 2 3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high frequency and low frequency clocks and switches the main system clock There are three operating modes Single clock mode dual clock mode and STOP mode These modes are controlled by ...

Page 136: ...t individual enable flag 1 and TBTCR TBTEN 1 interrupt pro cessing is performed When IDLE0 mode is entered while TBTCR TBTEN 1 the INTTBT interrupt latch is set after returning to NORMAL1 mode 2 2 3 2 Dual clock mode Both the high frequency and low frequency oscillation circuits are used in this mode P21 XTIN and P22 XTOUT pins cannot be used as input output ports The main system clock is obtained...

Page 137: ...he SLEEP1 mode except for the oscillation circuit of the high frequency clock 7 SLEEP0 mode In this mode all the circuit except oscillator and the timer base timer stops operation This mode is enabled by setting 1 on bit SYSCR2 TGHALT When SLEEP0 mode starts the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT Then upon detecting the falling edge...

Page 138: ...Operate Operate IDLE1 Halt IDLE0 Halt STOP Stop Halt Dual clock NORMAL2 Oscillation Oscillation Operate with high frequency Operate Operate 4 fc s IDLE2 Halt SLOW2 Operate with low frequency 4 fs s SLEEP2 Halt SLOW1 Stop Operate with low frequency SLEEP1 Halt SLEEP0 Halt STOP Stop Halt Note 2 SYSCR2 XEN 1 STOP pin input STOP pin input STOP pin input Interrupt Interrupt SYSCR2 XEN 0 SYSCR2 SYSCK 1 ...

Page 139: ...EEP0 mode is released TGHALT is automatically cleared to 0 Note 8 Before setting TGHALT to 1 be sure to stop peripherals If peripherals are not stopped the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released System Control Register 1 SYSCR1 7 6 5 4 3 2 1 0 0038H STOP RELM RETM OUTEN WUT Initial value 0000 00 STOP STOP mode start 0 CPU core and peripherals remain active...

Page 140: ... release input the STOP pin must be used for releasing STOP mode Note 2 During STOP period from start of STOP mode to end of warm up due to changes in the external interrupt pin signal interrupt latches may be set to 1 and interrupts may be accepted immediately after STOP mode is released Before starting STOP mode therefore disable interrupts Also before enabling interrupts after STOP mode is rele...

Page 141: ...y STOP3 to STOP0 pin input for releasing STOP mode in edge sensitive release mode Figure 2 8 Edge sensitive Release Mode Example 2 Starting STOP mode from NORMAL mode with an INT5 interrupt PINT5 TEST P2PRD 0 To reject noise STOP mode does not start if JRS F SINT5 port P20 is at high LD SYSCR1 01010000B Sets up the level sensitive release mode DI IMF 0 SET SYSCR1 7 Starts STOP mode SINT5 RETI Exam...

Page 142: ...low level on the RESET pin which immediately performs the normal reset operation Note 3 When STOP mode is released with a low hold voltage the following cautions must be observed The power supply voltage must be at the operating voltage level before releasing STOP mode The RESET pin input must also be H level rising together with the power supply voltage In this case if an external time constant c...

Page 143: ... start Example Start with SET SYSCR1 7 instruction located at address a a 6 a 5 a 4 a 3 a 2 n 2 n 3 n 4 a 3 n 1 Instruction address a 2 2 1 0 3 b STOP mode release Count up Turn off Halt Oscillator circuit Program counter Instruction execution Divider Main system clock Oscillator circuit STOP pin input Program counter Instruction execution Divider Main system clock ...

Page 144: ...2 The data memory CPU registers program status word and port output latches are all held in the status in effect before these modes were entered 3 The program counter holds the address 2 ahead of the instruction which starts these modes Figure 2 10 IDLE1 2 and SLEEP1 2 Modes Reset Reset input 0 1 Interrupt release mode Yes No No CPU and WDT are halted Interrupt request IMF Interrupt processing Nor...

Page 145: ...elease mode IMF 0 IDLE1 2 and SLEEP1 2 modes are released by any interrupt source enabled by the individual interrupt enable flag EF After the interrupt is generated the program operation is resumed from the instruction following the IDLE1 2 and SLEEP1 2 modes start instruction Normally the interrupt latches IL of the interrupt source used for releasing must be cleared to 0 by load instructions 2 ...

Page 146: ...rrupt 㽲㩷Normal release mode 㽳㩷Interrupt release mode Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock Interrupt request Program counter Instruction execution Watchdog timer a IDLE1 2 and SLEEP1 2 modes start Example Starting with the SET instruction loc...

Page 147: ...fore IDLE0 and SLEEP0 modes were entered 3 The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes Note Before starting IDLE0 or SLEEP0 mode be sure to stop Disable peripherals Figure 2 12 IDLE0 and SLEEP0 Modes Yes Normal release mode Yes Interrupt release mode No Yes Reset input CPU and WDT are halted Reset TBT source clock falling edge TBTCR TBTEN 1 ...

Page 148: ...Note IDLE0 and SLEEP0 modes start release without reference to TBTCR TBTEN setting 1 Normal release mode IMF EF7 TBTCR TBTEN 0 IDLE0 and SLEEP0 modes are released by the source clock falling edge which is setting by the TBTCR TBTCK After the falling edge is detected the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction Before starting the IDLE...

Page 149: ...release mode Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock TBT clock TBT clock Program counter Instruction execution Watchdog timer Main system clock Program counter Instruction execution Watchdog timer a 3 a 2 a 4 a 3 a 3 a IDLE0 and SLEEP0 modes start Example Starting with the SET instruction located at address a b IDLE and SLEEP0 mode...

Page 150: ...g from SLOW mode to stop mode Example 1 Switching from NORMAL2 mode to SLOW1 mode SET SYSCR2 5 SYSCR2 SYSCK 1 Switches the main system clock to the low frequency clock for SLOW2 CLR SYSCR2 7 SYSCR2 XEN 0 Turns off high frequency oscillation Example 2 Switching to the SLOW1 mode after low frequency clock has stabilized SET SYSCR2 6 SYSCR2 XTEN 1 LD TC5CR 43H Sets mode for TC6 5 16 bit mode fs for s...

Page 151: ... inputting low level on the RESET pin After releasing reset the operation mode is started from NORMAL1 mode Example Switching from the SLOW1 mode to the NORMAL2 mode fc 16 MHz warm up time is 4 0 ms SET SYSCR2 7 SYSCR2 XEN 1 Starts high frequency oscillation LD TC5CR 63H Sets mode for TC6 5 16 bit mode fc for source LD TC6CR 05H Sets warming up counter mode LD TTREG6 0F8H Sets warm up time DI IMF ...

Page 152: ...YSCR2 7 SET SYSCR2 5 NORMAL2 mode Turn off a Switching to the SLOW mode SLOW1 mode SLOW2 mode CLR SYSCR2 5 b Switching to the NORMAL2 mode High frequency clock Low frequency clock Main system clock Instruction execution SYSCK XEN High frequency clock Low frequency clock Main system clock Instruction execution SYSCK XEN SLOW1 mode Warm up during SLOW2 mode ...

Page 153: ...g voltage range and oscillation stable a reset is applied and the internal state is initial ized When the RESET pin input goes high the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH Figure 2 15 Reset Circuit Table 2 3 Initializing Internal Status by Reset Action On chip Hardware Initial Value On chip Hardware Initial Value Pro...

Page 154: ...et release reset vector r is read out and an instruction at address r is fetched and decoded Figure 2 16 Address Trap Reset 2 3 3 Watchdog timer reset Refer to Section Watchdog Timer 2 3 4 System clock reset If the condition as follows is detected the system clock reset occurs automatically to prevent dead lock of the CPU The oscillation is continued without stopping In case of clearing SYSCR2 XEN...

Page 155: ...Page 33 T5CL8 ...

Page 156: ...Page 34 2 Operational Description 2 3 Reset Circuit T5CL8 ...

Page 157: ...er 3 1 Interrupt latches IL23 to IL2 An interrupt latch is provided for each interrupt source except for a software interrupt and an executed the unde fined instruction interrupt When interrupt request is generated the latch is set to 1 and the CPU is requested to accept the interrupt if its interrupt is enabled The interrupt latch is cleared to 0 immediately after accepting inter rupt All interru...

Page 158: ...he non maskable interrupts Software interrupt undefined instruction interrupt address trap interrupt and watchdog interrupt Non maskable interrupt is accepted regardless of the contents of the EIR The EIR consists of an interrupt master enable flag IMF and the individual interrupt enable flags EF These registers are located on address 002CH 003AH and 003BH in SFR area and they can be read and writ...

Page 159: ... EF or the interrupt latch IL be sure to clear IMF to 0 Disable interrupt by DI instruction Then set IMF newly again as required after operating on the EF or IL Enable interrupt by EI instruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute nor mally on interrupt service routine However if using multiple interrupt on interrupt service routine m...

Page 160: ...nstruction In interrupt service routine because the IMF becomes 0 automatically clearing IMF need not execute normally on inter rupt service routine However if using multiple interrupt on interrupt service routine manipulating EF or IL should be exe cuted before setting IMF 1 Interrupt Latches Initial value 00000000 000000 ILH ILL 003DH 003CH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IL15 IL14 IL13 IL...

Page 161: ...ector of the corresponding interrupt service program loaded on the vec tor table is transferred to the program counter e The instruction stored at the entry address of the interrupt service program is executed Note When the contents of PSW are saved on the stack the contents of IMF are also saved Note 1 a Return address entry address b Entry address c Address which RETI instruction is stored Note ...

Page 162: ...s IMF are automatically saved on the stack but the accumulator and others are not These registers are saved by software if necessary When multiple interrupt services are nested it is also necessary to avoid using the same data memory area for saving registers The following methods are used to save restore the general purpose registers 3 3 2 1 Using PUSH and POP instructions If only a specific regi...

Page 163: ...are located on address SP 1 and SP 2 respectively Example Save store register using data transfer instructions PINTxx LD GSAVA A Save A register interrupt processing LD A GSAVA Restore A register RETI RETURN RETI RETN Interrupt Return 1 Program counter PC and program status word PSW includes IMF are restored from the stack 2 Stack pointer SP is incremented by 3 Example 1 Returning from address tra...

Page 164: ...ress trap reset is generated in case that an instruction is fetched from RAM DBR or SFR areas 3 4 2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address 3 5 Undefined Instruction Interrupt INTUNDEF Taking code which is not defined as authorized instruction for instruction causes INTUNDEF INTUNDEF is gen erated when the CPU fetch...

Page 165: ...lling edge Pulses of less than 2 fc s are eliminated as noise Pulses of 7 fc s or more are considered to be signals In the SLOW or the SLEEP mode pulses of less than 1 fs s are eliminated as noise Pulses of 3 5 fs s or more are consid ered to be signals INT1 INT1 IMF EF6 1 Falling edge or Rising edge Pulses of less than 15 fc or 63 fc s are elimi nated as noise Pulses of 49 fc or 193 fc s or more ...

Page 166: ... from modifying INT1NC until a noise reject time is changed is 26 fc External Interrupt Control Register EINTCR 7 6 5 4 3 2 1 0 0037H INT1NC INT0EN INT3ES INT2ES INT1ES Initial value 00 000 INT1NC Noise reject time select 0 Pulses of less than 63 fc s are eliminated as noise 1 Pulses of less than 15 fc s are eliminated as noise R W INT0EN P00 INT0 pin configuration 0 P00 input output port 1 INT0 p...

Page 167: ...ion register SFR and data buffer register DBR for T5CL8 4 1 SFR Address Read Write 0000H P0DR 0001H P1DR 0002H P2DR 0003H P3DR 0004H P4DR 0005H P5DR 0006H P6DR 0007H P7DR 0008H P0OUTCR 0009H P1CR 000AH P4OUTCR 000BH P0PRD 000CH P2PRD 000DH P3PRD 000EH P4PRD 000FH P5PRD 0010H TC1DRAL 0011H TC1DRAH 0012H TC1DRBL 0013H TC1DRBH 0014H TTREG3 0015H TTREG4 0016H TTREG5 0017H TTREG6 0018H PWREG3 0019H PWR...

Page 168: ...ion instructions such as SET CLR etc and logical operation instructions such as AND OR etc 0026H TC1CR 0027H TC3CR 0028H TC4CR 0029H TC5CR 002AH TC6CR 002BH SIO2RDB SIO2TDB 002CH EIRE 002DH Reserved 002EH ILE 002FH Reserved 0030H Reserved 0031H SIO2CR 0032H SIO2SR 0033H Reserved 0034H WDTCR1 0035H WDTCR2 0036H TBTCR 0037H EINTCR 0038H SYSCR1 0039H SYSCR2 003AH EIRL 003BH EIRH 003CH ILL 003DH ILH 0...

Page 169: ...ved 0F8CH Reserved 0F8DH Reserved 0F8EH Reserved 0F8FH Reserved 0F90H SBISRA SBICRA 0F91H SBIDBR 0F92H I2CAR 0F93H SBISRB SBICRB 0F94H Reserved 0F95H UART1SR UART1CR1 0F96H UART1CR2 0F97H RD1BUF TD1BUF 0F98H UART2SR UART2CR1 0F99H UART2CR2 0F9AH RD2BUF TD2BUF 0F9BH P6CR1 0F9CH P6CR2 0F9DH P7CR1 0F9EH P7CR2 0F9FH STOPCR Address Read Write 0FA0H Reserved 0FBFH Reserved Address Read Write 0FC0H Reser...

Page 170: ...such as AND OR etc Address Read Write 0FE0H Reserved 0FE1H Reserved 0FE2H Reserved 0FE3H Reserved 0FE4H Reserved 0FE5H Reserved 0FE6H Reserved 0FE7H Reserved 0FE8H Reserved 0FE9H Reserved 0FEAH Reserved 0FEBH Reserved 0FECH Reserved 0FEDH Reserved 0FEEH Reserved 0FEFH Reserved 0FF0H Reserved 0FF1H Reserved 0FF2H Reserved 0FF3H Reserved 0FF4H Reserved 0FF5H Reserved 0FF6H Reserved 0FF7H Reserved 0F...

Page 171: ...y vary depending on the instruction Figure 5 1 Input Output Timing Example Primary Function Secondary Functions Port P0 8 bit I O port External interrupt Serial PROM mode cotrol input serial interface input output UART input output Port P1 8 bit I O port External interrupt timer counter input output divider output Port P2 3 bit I O port Low frequency resonator connections external interrupt input ...

Page 172: ...e output circuit is selected to a C MOS output When used as an input port an external interrupt input a serial interface input and an UART input the correspond ing output control P0OUTCR should be set to 0 after P0DR is set to 1 P0 port output latch P0DR and P0 port terminal input P0PRD are located on their respective address When read the output latch data the P0DR should be read When read the te...

Page 173: ...4 SI1 P03 INT1 P02 TXD1 P01 RXD1 BOOT P00 INT0 Initial value 1111 1111 P0OUTCR 0008H Initial value 0000 0000 P0OUTCR Port P0 output circuit control Set for each bit individually 0 Sink open drain output 1 C MOS output R W P0PRD 000BH Read only P07 P06 P05 P04 P03 P02 P01 P00 ...

Page 174: ...tput and a divider output P1DR is set to 1 beforehand and the corresponding bit of P1CR should be set to 1 When P1CR is 1 the content of the corresponding output latch is read by reading P1DR Note Asterisk indicates 1 or 0 either of which can be selected Note i 7 to 0 Figure 5 3 Port 1 and P1CR Note The port set to an input mode reads the terminal input data Therefore when the input and output mod...

Page 175: ...O6 PPG6 P16 TC5 PWM5 PDO5 P15 TC2 INT3 P14 TC4 PWM4 PDO4 PPG4 P13 TC3 PWM3 PDO3 P12 PPG P11 DVO P10 TC1 Initial value 0000 0000 P1CR 0009H 7 6 5 4 3 2 1 0 Initial value 0000 0000 P1CR I O control for port P1 Specified for each bit 0 Input mode 1 Output mode R W ...

Page 176: ... port the interrupt latch is set on the falling edge of the output pulse P2 port output latch P2DR and P2 port terminal input P2PRD are located on their respective address When read the output latch data the P2DR should be read and when read the terminal input data the P2PRD reg ister should be read If a read instruction is executed for port P2 read data of bits 7 to 3 are unstable Figure 5 4 Port...

Page 177: ...and P3 port terminal input P3PRD are located on their respective address When read the output latch data the P3DR should be read When read the terminal input data the P3PRD register should be read Note i 7 to 0 Figure 5 5 Port 3 P3DR 0003H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 1111 1111 R W P3PRD 000DH Read only P37 P36 P35 P34 P33 P32 P31 P30 Data output P3DR STOP OUTEN D ...

Page 178: ... 1 the output circuit is selected to a C MOS output When used as an input port a serial interface input and an UART input the corresponding output control P4OUTCR should be set to 0 after P4DR is set to 1 P4 port output latch P4DR and P4 port terminal input P4PRD are located on their respective address When read the output latch data the P4DR should be read When read the terminal input data the P4...

Page 179: ...O2 P44 SI2 P43 P42 TXD2 P41 RXD2 P40 Initial value 1111 1111 P4OUTCR 000AH Initial value 0000 0000 P4OUTCR Port P4 output circuit control Set for each bit individually 0 Sink open drain output 1 C MOS output R W P4PRD 000EH Read only P47 P46 P45 P44 P43 P42 P41 P40 ...

Page 180: ...latch P5DR and P5 port terminal input P5PRD are located on their respective address When read the output latch data the P5DR should be read When read the terminal input data the P5PRD register should be read If a read instruction is executed for port P5 read data of bit 7 to 5 are unstable Note i 4 to 0 Figure 5 7 Port 5 P5DR 0005H R W 7 6 5 4 3 2 1 0 P54 P53 P52 P51 SDA P50 SCL Initial value 1 11...

Page 181: ...bit of P6CR2 should be set to 1 When used as a key on wakeup input the corresponding bit of P6CR1 should be set to 0 and then the corre sponding bit of STOPkEN should be set to 1 When used as an analog input the corresponding bit of P6CR1 should be set to 0 and then the corresponding bit of P6CR2 should be set to 0 When P6CR1 is 1 the content of the corresponding output latch is read by reading P6...

Page 182: ...ect signal in a key on wakeup Figure 5 8 Port 6 P6CR1 and P6CR2 P6i D Q D Q P6CR2i P6CR2i input P6CR1i P6CR1i input Data input P6DRi Data output P6DRi STOP OUTTEN Analog input AINDS SAIN D Q Control input P6j D Q D Q P6CR2j P6CR2j input P6CR1j P6CR1j input Data output P6DRj STOP OUTTEN Analog input AINDS STOPkEN Key on wakeup D Q Data input P6DRj a P63 to P60 SAIN b P67 to P64 ...

Page 183: ...sed for analog input can be used as I O ports During AD conversion output instructions should not be executed to keep a precision In addition a variable signal should not be input to a port adjacent to the analog input during AD con version P6DR 0006H R W 7 6 5 4 3 2 1 0 P67 AIN7 STOP3 P66 AIN6 STOP2 P65 AIN5 STOP1 P64 AIN4 STOP0 P63 AIN3 P62 AIN2 P61 AIN1 P60 AIN0 Initial value 0000 0000 P6CR1 0F...

Page 184: ... as an input port the corresponding bit of P7CR1 should be set to 0 and then the corresponding bit of P7CR2 should be set to 1 When used as an analog input the corresponding bit of P7CR1 should be set to 0 and then the corresponding bit of P7CR2 should be set to 0 When P7CR1 is 1 the content of the corresponding output latch is read by reading P7DR Note Asterisk indicates 1 or 0 either of which ca...

Page 185: ...d for analog input can be used as I O ports During AD conversion output instructions should not be executed to keep a precision In addition a variable signal should not be input to a port adjacent to the analog input during AD con version P7DR 0007H R W 7 6 5 4 3 2 1 0 P77 AIN15 P76 AIN14 P75 AIN13 P74 AIN12 P73 AIN11 P72 AIN10 P71 AIN9 P70 AIN8 Initial value 0000 0000 P7CR1 0F9DH 7 6 5 4 3 2 1 0 ...

Page 186: ...Page 64 5 I O Ports 5 8 Port P7 P77 to P70 T5CL8 ...

Page 187: ...sed to detect malfunctions it can be used as the timer to provide a periodic inter rupt Note Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise 6 1 Watchdog Timer Configuration Figure 6 1 Watchdog Timer Configuration 0034H Overflow WDT output Internal reset Binary counters WDTOUT Writing clear code Writing disable...

Page 188: ...T is generated The watchdog timer temporarily stops counting in the STOP mode including the warm up or IDLE SLEEP mode and automatically restarts continues counting when the STOP IDLE SLEEP mode is inactivated Note The watchdog timer consists of an internal divider and a two stage binary counter When the clear code 4EH is written only the binary counter is cleared but not the internal divider The ...

Page 189: ...ycle shorter than 3 4 of the time set in WDTCR1 WDTT 6 2 2 Watchdog Timer Enable Setting WDTCR1 WDTEN to 1 enables the watchdog timer Since WDTCR1 WDTEN is initialized to 1 during reset the watchdog timer is enabled automatically after the reset release Watchdog Timer Control Register 1 WDTCR1 0034H 7 6 5 4 3 2 1 0 ATAS ATOUT WDTEN WDTT WDTOUT Initial value 11 1001 WDTEN Watchdog timer enable disa...

Page 190: ...ag IMF When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending Therefore if watchdog timer interrupts are generated continuously without execution of the RETN instruction too many levels of nesting may cause a malfunction of th...

Page 191: ...nerated in the SLOW1 mode the reset time is maximum 24 fc high fre quency clock since the high frequency clock oscillator is restarted However when crystals have inaccura cies upon start of the high frequency clock oscillator the reset time should be considered as an approximate value because it has slight errors Figure 6 2 Watchdog Timer Interrupt Clock Binary counter Overflow INTWDT interrupt re...

Page 192: ...is a non maskable interrupt which can be accepted regardless of the interrupt mas ter flag IMF When an address trap interrupt is generated while the other interrupt including an address trap interrupt is already accepted the new address trap is processed immediately and the previous interrupt is held pending Therefore if address trap interrupts are generated continuously without execution of the R...

Page 193: ...an address trap reset request is generated the internal hardware is reset The reset time is maximum 24 fc s 1 5 µs fc 16 0 MHz Note When an address trap reset is generated in the SLOW1 mode the reset time is maximum 24 fc high fre quency clock since the high frequency clock oscillator is restarted However when crystals have inaccura cies upon start of the high frequency clock oscillator the reset ...

Page 194: ...Page 72 6 Watchdog Timer WDT 6 3 Address Trap T5CL8 ...

Page 195: ...CR 0036H DVOEN DVOCK DV7CK TBTEN TBTCK Initial Value 0000 0000 TBTEN Time Base Timer enable disable 0 Disable 1 Enable TBTCK Time Base Timer interrupt Frequency select Hz NORMAL1 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 Mode R W DV7CK 0 DV7CK 1 000 fc 223 fs 215 fs 215 001 fc 221 fs 213 fs 213 010 fc 216 fs 28 011 fc 214 fs 26 100 fc 213 fs 25 101 fc 212 fs 24 110 fc 211 fs 23 111 fc 29 fs 2 fc 223 or fs 2...

Page 196: ...e divider is not cleared by the program therefore only the first interrupt may be generated ahead of the set interrupt period Figure 7 2 Figure 7 2 Time Base Timer Interrupt Example Set the time base timer frequency to fc 216 Hz and enable an INTTBT interrupt LD TBTCR 00000010B TBTCK 010 LD TBTCR 00001010B TBTEN 1 DI IMF 0 SET EIRL 7 Table 7 1 Time Base Timer Interrupt Frequency Example fc 16 0 MH...

Page 197: ...abled DVOEN 1 to disable DVOEN 0 do not change the setting of the divider output frequency Time Base Timer Control Register 7 6 5 4 3 2 1 0 TBTCR 0036H DVOEN DVOCK DV7CK TBTEN TBTCK Initial value 0000 0000 DVOEN Divider output enable disable 0 Disable 1 Enable R W DVOCK Divider Output DVO frequency selection Hz NORMAL1 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 Mode R W DV7CK 0 DV7CK 1 00 fc 213 fs 25 fs 25 ...

Page 198: ...00000B DVOCK 00 LD TBTCR 10000000B DVOEN 1 Table 7 2 Divider Output Frequency Example fc 16 0 MHz fs 32 768 kHz DVOCK Divider Output Frequency Hz NORMAL1 2 IDLE1 2 Mode SLOW1 2 SLEEP1 2 Mode DV7CK 0 DV7CK 1 00 1 953 k 1 024 k 1 024 k 01 3 906 k 2 048 k 2 048 k 10 7 813 k 4 096 k 4 096 k 11 15 625 k 8 192 k 8 192 k ...

Page 199: ... Window mode Set Toggle Q 2 Toggle Set Clear Q Y A D B C S B A Y S TC1S clear MPPG1 PPG output mode Internal reset S Enable MCAP1 S Y A B TC1S 2 Set Clear Command start Decoder External trigger start Edge detector Note Function I O may not operate depending on I O port setting For more details see the chapter I O Port Port Note Q Pulse width measurement mode Falling Rising trigger External CMP 16 ...

Page 200: ...1DRBL 0012H Initial value 1111 1111 1111 1111 Read Write Write enabled only in the PPG output mode TimerCounter 1 Control Register TC1CR 0026H 7 6 5 4 3 2 1 0 TFF1 ACAP1 MCAP1 METT1 MPPG1 TC1S TC1CK TC1M Read Write Initial value 0000 0000 TFF1 Timer F F1 control 0 Clear 1 Set R W ACAP1 Auto capture control 0 Auto capture disable 1 Auto capture enable R W MCAP1 Pulse width measure ment mode control...

Page 201: ...leared to 00 automatically and the timer stops After the STOP mode is exited set the TC1S to use the timer counter again Note 9 Use the auto capture function in the operative condition of TC1 A captured value may not be fixed if it s read after the execution of the timer stop or auto capture disable Read the capture value in a capture enabled condition Note 10 Since the up counter value is capture...

Page 202: ...after setting TC1CR ACAP1 to 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading TC1DRB for the first time Note Since the up counter value is captured into TC1DRB by the source clock of up counter after setting TC1CR ACAP1 to 1 Therefore to read the captured value wait at least one cycle of the internal source clock before reading TC1DRB for t...

Page 203: ...ch detect ACAP1 TC1DRB TC1DRA INTTC1 interruput request Source clock Counter Source clock Counter a Timer mode b Auto capture 7 6 3 4 5 0 Timer start 1 2 3 2 1 4 0 Counter clear Capture n 1 n n n m 2 m 1 m m Capture m 2 m 1 n 1 n m 1 m 1 m 2 n 1 n 1 n 1 ...

Page 204: ...TC1DRA value is detected after the timer starts the up counter is cleared and halted and an INTTC1 interrupt request is generated The edge opposite to the trigger edge has no effect in count up The trigger edge for the next count ing is ignored if detecting it before detecting a match between the up counter and the TC1DRA Since the TC1 pin input has the noise rejection pulses of 4 fc s or less are...

Page 205: ...nterrupt request Source clock Up counter TC1DRA TC1 pin input 0 At the rising edge TC1S 10 At the rising edge TC1S 10 a Trigger start METT1 0 Count start Match detect Count start 0 1 2 3 4 2 3 n b Trigger start and stop METT1 1 Count start Count start 0 1 2 3 m 0 n n 0 Count clear Note m n Count clear 1 2 3 1 n m 1 n 1 Match detect Count clear ...

Page 206: ...required for the low or high level pulse input to the TC1 pin Setting TC1CR ACAP1 to 1 captures the up counter value into TC1DRB with the auto capture function Use the auto capture function in the operative condition of TC1 A captured value may not be fixed if it s read after the execution of the timer stop or auto capture disable Read the capture value in a capture enabled condi tion Since the up...

Page 207: ... INTTC1 interrupt is generated and the up counter is cleared Define the window pulse to the frequency which is sufficiently lower than the internal source clock pro grammed with TC1CR TC1CK Figure 8 5 Window Mode Timing Chart Match detect TC1DRA INTTC1 interrput request interrput request Internal clock Counter TC1DRA TC1 pin input Internal clock Counter TC1 pin input INTTC1 a Positive logic TC1S 1...

Page 208: ...ycle starting with either the high or low going input pulse can be measured To measure the cycle starting with the high going pulse set the rising edge to TC1CR TC1S To measure the cycle starting with the low going pulse set the falling edge to TC1CR TC1S When detecting the edge opposite to the trigger edge used to start counting after the timer starts the up counter captures the up counter value ...

Page 209: ...100110B Starts TC1 with an external trigger at MCAP1 0 PINTTC1 CPL INTTC1SW 0 INTTC1 interrupt inverts and tests INTTC1 service switch JRS F SINTTC1 LD A TC1DRBL Reads TC1DRB High level pulse width LD W TC1DRBH LD HPULSE WA Stores high level pulse width in RAM RETI SINTTC1 LD A TC1DRBL Reads TC1DRB Cycle LD W TC1DRBH LD WIDTH WA Stores cycle in RAM RETI Duty calculation VINTTC1 DW PINTTC1 INTTC1 I...

Page 210: ...1 2 3 n Count start Count start Trigger TC1S 10 1 3 2 1 4 0 n 0 Capture n 1 TC1DRB INTTC1 TC1 pin input Counter Internal clock MCAP1 0 1 2 n Count start Count start TC1S 10 3 2 1 4 0 n Capture Capture n 1 m 2 n 3 n 2 n 1 m 1 m 0 m Application High or low level pulse width measurement Application 1 Cycle frequency measurement 2 Duty measurement a Single edge capture b Double edge capture ...

Page 211: ...t request is generated TC1CR TC1S is cleared to 00 automatically at this time and the timer stops The pulse generated by PPG retains the same level as that when the timer stops Since the output level of the PPG pin can be set with TC1CR TFF1 when the timer starts a positive or neg ative pulse can be generated Since the inverted level of the timer F F1 output level is output to the PPG pin specify ...

Page 212: ...el to restart PPG fc 16 MHz Setting port LD TC1CR 10000111B Sets the PPG mode selects the source clock LDW TC1DRA 007DH Sets the cycle 1 ms 27 fc µs 007DH LDW TC1DRB 0019H Sets the low level pulse width 200 µs 27 fc 0019H LD TC1CR 10010111B Starts the timer LD TC1CR 10000111B Stops the timer LD TC1CR 10000100B Sets the timer mode LD TC1CR 00000111B Sets the PPG mode TFF1 0 LD TC1CR 00010111B Start...

Page 213: ...1 interrupt request interrupt request 1 2 m 0 1 2 n m 0 1 n 2 n n 1 n 1 m a Continuous pulse generation TC1S 01 TC1DRB Trigger Count start Timer start Counter Internal clock TC1 pin input PPG pin output 0 1 m n n n 1 m 0 b One shot pulse generation TC1S 10 Match detect Note m n Note m n Application One shot pulse output ...

Page 214: ...Page 92 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 ...

Page 215: ...ectly For details refer to the section I O ports Figure 9 1 Timer Counter2 TC2 C D F TC2 control register TC2 pin TC2CR 16 bit up counter TC2DR Clear TC2S TC2CK Source clock Timer event counter Window TC2S 16 bit timer register 2 3 H A B E S B A S Y INTTC2 interrupt Port Note CMP TC2M fc fs Match fc 223 fs 215 fc 28 fc 23 fc 213 fs 25 ...

Page 216: ...C2DR11 1 at warm up Note 6 If a read instruction is executed for TC2CR read data of bit 7 6 and 1 are unstable Note 7 The high frequency clock fc canbe selected only when the time mode at SLOW2 mode is selected Note 8 On entering STOP mode the TC2 start control TC2S is cleared to 0 automatically So the timer stops Once the STOP mode has been released to start using the timer counter set TC2S again...

Page 217: ... necessary to set TC2DRH only Note When fc is selected as the source clock in timer mode it is used at warm up for switching from SLOW1 mode to NORMAL2 mode Table 9 1 Source Clock Internal clock for Timer Counter2 at fc 16 MHz DV7CK 0 TC2C K NORMAL1 2 IDLE1 2 mode SLOW1 2 mode SLEEP1 2 mode DV7CK 0 DV7CK 1 Resolution Maximum Time Set ting Resolution Maximum Time Set ting Resolu tion Maxi mum Time ...

Page 218: ...Page 96 9 16 Bit Timer Counter2 TC2 9 3 Function T5CL8 Figure 9 2 Timer Mode Timing Chart INTTC2 interrupt Source clock Up counter TC2DR Match detect Counter clear Timer start 0 1 2 3 4 n 0 1 2 3 㫅 ...

Page 219: ...ternal pin input Window pulse is H level The contents of TC2DR are compared with the contents of up counter If a match found an INTTC2 interrupt is generated and the up counter is cleared The maximum applied frequency TC2 input must be considerably slower than the selected internal clock by the TC2CR TC2CK Note It is not available window mode in the SLOW SLEEP mode Therefore at the window mode in ...

Page 220: ...e width of 120 ms or more at fc 16 MHz TBTCR DV7CK 0 LDW TC2DR 00EAH Sets TC2DR 120 ms 213 fc 00EAH DI IMF 0 SET EIRE 6 Enables INTTC2 interrupt EI IMF 1 LD TC2CR 00000101B TC2sorce clock mode select LD TC2CR 00100101B Starts TC2 Match detect 㫅㪇 INTTC2 interrupt Internal clock Counter TC2DR TC2 pin input Counter clear 1 2 3 n 0 1 2 Timer start ...

Page 221: ... PWM mode 16 bit mode 16 bit mode 16 bit mode 16 bit mode Timer Event Counter mode Overflow Overflow Timer Event Couter mode 16 bit mode Clear Clear fc 27 fc 2 5 fc 23 fc 2 fc fc 27 fc 2 5 fc 2 3 fc 2 fc PDO PWM PPG mode PDO PWM mode 16 bit mode fc 211 or fs 23 fc 211 or fs 23 fs fs TC4CR TC3CR TTREG4 PWREG4 TTREG3 PWREG3 TC3 pin TC4 pin TC4S TC3S INTTC3 interrupt request INTTC4 interrupt request ...

Page 222: ...select the source clock by programming TC3CK Set the timer start control and timer F F control by programming TC4CR TC4S and TC4CR TFF4 respectively Note 6 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 1 and Table 10 2 TimerCounter 3 Timer Register TTREG3 0014H R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 PWREG3 0018H R W 7...

Page 223: ... timer register settings are limited depending on the timer operating mode For the detailed descriptions see Table 10 3 Note 8 The operating clock fc in the SLOW or SLEEP mode can be used only as the high frequency warm up mode ...

Page 224: ...etting Note 5 To use the TimerCounter in the 16 bit mode select the operating mode by programming TC4M where TC3CR TC3M must be set to 011 TimerCounter 4 Timer Register TTREG4 0015H R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 PWREG4 0019H R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 TimerCounter 4 Control Register TC4CR 0028H 7 6 5 4 3 2 1 0 TFF4 TC4CK TC4S TC4M Initial value 0000 0000 TFF4 Timer F...

Page 225: ...able 10 1 Operating Mode and Selectable Source Clock NORMAL1 2 and IDLE1 2 Modes Operating mode fc 211 or fs 23 fc 27 fc 25 fc 23 fs fc 2 fc TC3 pin input TC4 pin input 8 bit timer Ο Ο Ο Ο 8 bit event counter Ο Ο 8 bit PDO Ο Ο Ο Ο 8 bit PWM Ο Ο Ο Ο Ο Ο Ο 16 bit timer Ο Ο Ο Ο 16 bit event counter Ο Warm up counter Ο 16 bit PWM Ο Ο Ο Ο Ο Ο Ο Ο 16 bit PPG Ο Ο Ο Ο Ο Table 10 2 Operating Mode and Selec...

Page 226: ...ster Values Being Compared Operating mode Register Value 8 bit timer event counter 1 TTREGn 255 8 bit PDO 1 TTREGn 255 8 bit PWM 2 PWREGn 254 16 bit timer event counter 1 TTREG4 3 65535 Warm up counter 256 TTREG4 3 65535 16 bit PWM 2 PWREG4 3 65534 16 bit PPG 1 PWREG4 3 TTREG4 3 65535 and PWREG4 3 1 TTREG4 3 ...

Page 227: ...tput pulses Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 3 4 Table 10 4 Source Clock for TimerC...

Page 228: ...REGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 3 4 Figure 10 3 8 Bit Event Counter Mode Timing Chart TC4 10 3 3 8 Bit Programmable Divider Output PDO Mode TC3 4 This mode is used to generate a pulse with a 50 duty cycle from the PDOj pin In the PDO mode the up counter counts up using t...

Page 229: ...the timer is stopped during PDO output the PDOj pin holds the output status when the timer is stopped To change the output status program TCjCR TFFj after the timer is stopped Do not change the TCjCR TFFj setting upon stopping of the timer Example Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the PDOj pin to the high level Note ...

Page 230: ...O Mode Timing Chart TC4 1 2 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n Internal source clock Counter Match detect Match detect Match detect Match detect Held at the level when the timer is stopped Set F F Write of 1 TC4CR TC4S TC4CR TFF4 TTREG4 Timer F F4 PDO4 pin INTTC4 interrupt request ...

Page 231: ...TCj is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREGj immediately after the INTTCj interrupt request is generated normally in the INTTCj interrupt service routine If the programming of PWREGj and the inter rupt request occur at the same time an unstable value is shifted that may result in generati...

Page 232: ... 1 0 n n 1 FF 0 n n 1 FF 0 1 m m 1 FF 0 1 1 p n Internal source clock Counter m p m p n Shift registar Shift Shift Shift Shift Match detect Match detect One cycle period Match detect Match detect n m p n TC4CR TC4S TC4CR TFF4 PWREG4 Timer F F4 PWM4 pin INTTC4 interrupt request Write to PWREG4 Write to PWREG4 ...

Page 233: ...iately after programming of TTREGj Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 j 3 4 Figure 10 6 16 Bit Timer Mode Timing Chart TC3 and TC4 Table 10 6 Source Clock for 16 Bit Timer Mode Source Clock Resolution Maximum Time Setting NORMAL1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 mode fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK...

Page 234: ...eading data of PWREG4 and 3 is previous value until INTTC4 is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated normally in the INTTC4 interrupt service routine If the programming of PWREGj and the interrupt request occur at the same t...

Page 235: ... 2 mode SLOW1 2 SLEEP1 2 mode fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 fc 211 fs 23 Hz fs 23 Hz 128 µs 244 14 µs 8 39 s 16 s fc 27 fc 27 8 µs 524 3 ms fc 25 fc 25 2 µs 131 1 ms fc 23 fc 23 500 ns 32 8 ms fs fs fs 30 5 µs 30 5 µs 2 s 2 s fc 2 fc 2 125 ns 8 2 ms fc fc 62 5 ns 4 1 ms Example Generating a pulse with 1 ms high level width and a period of 32 768 ms fc 16 0 MHz Set...

Page 236: ...1 FFFF 0 bm cp b c 1 1 cp n a an Internal source clock 16 bit shift register Shift Shift Shift Shift Counter Match detect Match detect One cycle period Match detect Match detect an bm cp an m p TC4CR TC4S TC4CR TFF4 PWREG3 Lower byte Timer F F4 PWM4 pin INTTC4 interrupt request PWREG4 Upper byte Write to PWREG4 Write to PWREG4 Write to PWREG3 Write to PWREG3 ...

Page 237: ...ote 1 In the PPG mode do not change the PWREGi and TTREGi settings while the timer is running Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode the new values pro grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi Therefore if PWREGi and TTREGi are changed while the timer is running an expected operation may not be obtained ...

Page 238: ...1 1 mn mn 1 mn 1 0 qr 0 qr 1 0 Internal source clock Counter Write of 0 Match detect Match detect Match detect mn mn mn Match detect Match detect n m r q Held at the level when the timer stops F F clear TC4CR TC4S TC4CR TFF4 PWREG3 Lower byte Timer F F4 PPG4 pin INTTC4 interrupt request PWREG4 Upper byte TTREG3 Lower byte TTREG4 Upper byte ...

Page 239: ... timer register TTREG4 3 value is detected after the timer is started by setting TC4CR TC4S to 1 the counter is cleared by generating the INTTC4 interrupt request After stopping the timer in the INTTC4 interrupt service routine set SYSCR2 SYSCK to 1 to switch the system clock from the high frequency to low frequency and then clear of SYSCR2 XEN to 0 to stop the high frequency clock Table 10 8 Sett...

Page 240: ...frequency to high frequency and then SYSCR2 XTEN to 0 to stop the low frequency clock Table 10 9 Setting Time in High Frequency Warm Up Counter Mode Minimum time Setting TTREG4 3 0100H Maximum time Setting TTREG4 3 FF00H 16 µs 4 08 ms Example After checking high frequency clock oscillation stability with TC4 and 3 switching to the NORMAL1 mode SET SYSCR2 7 SYSCR2 XEN 1 LD TC3CR 63H Sets TFF3 0 sou...

Page 241: ... PWM mode 16 bit mode 16 bit mode 16 bit mode 16 bit mode Timer Event Counter mode Overflow Overflow Timer Event Couter mode 16 bit mode Clear Clear fc 27 fc 2 5 fc 23 fc 2 fc fc 27 fc 2 5 fc 2 3 fc 2 fc PDO PWM PPG mode PDO PWM mode 16 bit mode fc 211 or fs 23 fc 211 or fs 23 fs fs TC6CR TC5CR TTREG6 PWREG6 TTREG5 PWREG5 TC5 pin TC6 pin TC6S TC5S INTTC5 interrupt request INTTC6 interrupt request ...

Page 242: ...select the source clock by programming TC5CK Set the timer start control and timer F F control by programming TC6CR TC6S and TC6CR TFF6 respectively Note 6 The operating clock settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 1 and Table 11 2 TimerCounter 5 Timer Register TTREG5 0016H R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 PWREG5 001AH R W 7...

Page 243: ... timer register settings are limited depending on the timer operating mode For the detailed descriptions see Table 11 3 Note 8 The operating clock fc in the SLOW or SLEEP mode can be used only as the high frequency warm up mode ...

Page 244: ...etting Note 5 To use the TimerCounter in the 16 bit mode select the operating mode by programming TC6M where TC5CR TC5M must be set to 011 TimerCounter 6 Timer Register TTREG6 0017H R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 PWREG6 001BH R W 7 6 5 4 3 2 1 0 Initial value 1111 1111 TimerCounter 6 Control Register TC6CR 002AH 7 6 5 4 3 2 1 0 TFF6 TC6CK TC6S TC6M Initial value 0000 0000 TFF6 Timer F...

Page 245: ...able 11 1 Operating Mode and Selectable Source Clock NORMAL1 2 and IDLE1 2 Modes Operating mode fc 211 or fs 23 fc 27 fc 25 fc 23 fs fc 2 fc TC5 pin input TC6 pin input 8 bit timer Ο Ο Ο Ο 8 bit event counter Ο Ο 8 bit PDO Ο Ο Ο Ο 8 bit PWM Ο Ο Ο Ο Ο Ο Ο 16 bit timer Ο Ο Ο Ο 16 bit event counter Ο Warm up counter Ο 16 bit PWM Ο Ο Ο Ο Ο Ο Ο Ο 16 bit PPG Ο Ο Ο Ο Ο Table 11 2 Operating Mode and Selec...

Page 246: ...ster Values Being Compared Operating mode Register Value 8 bit timer event counter 1 TTREGn 255 8 bit PDO 1 TTREGn 255 8 bit PWM 2 PWREGn 254 16 bit timer event counter 1 TTREG6 5 65535 Warm up counter 256 TTREG6 5 65535 16 bit PWM 2 PWREG6 5 65534 16 bit PPG 1 PWREG6 5 TTREG6 5 65535 and PWREG6 5 1 TTREG6 5 ...

Page 247: ...tput pulses Note 2 In the timer mode do not change the TTREGj setting while the timer is running Since TTREGj is not in the shift register configuration in the timer mode the new value programmed in TTREGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 5 6 Table 11 4 Source Clock for TimerC...

Page 248: ...REGj is in effect immediately after the programming Therefore if TTREGi is changed while the timer is running an expected operation may not be obtained Note 3 j 5 6 Figure 11 3 8 Bit Event Counter Mode Timing Chart TC6 11 3 3 8 Bit Programmable Divider Output PDO Mode TC5 6 This mode is used to generate a pulse with a 50 duty cycle from the PDOj pin In the PDO mode the up counter counts up using t...

Page 249: ...the timer is stopped during PDO output the PDOj pin holds the output status when the timer is stopped To change the output status program TCjCR TFFj after the timer is stopped Do not change the TCjCR TFFj setting upon stopping of the timer Example Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR TCjCR 3 Stops the timer CLR TCjCR 7 Sets the PDOj pin to the high level Note ...

Page 250: ...O Mode Timing Chart TC6 1 2 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n Internal source clock Counter Match detect Match detect Match detect Match detect Held at the level when the timer is stopped Set F F Write of 1 TC6CR TC6S TC6CR TFF6 TTREG6 Timer F F6 PDO6 pin INTTC6 interrupt request ...

Page 251: ...TCj is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREGj immediately after the INTTCj interrupt request is generated normally in the INTTCj interrupt service routine If the programming of PWREGj and the inter rupt request occur at the same time an unstable value is shifted that may result in generati...

Page 252: ... 1 0 n n 1 FF 0 n n 1 FF 0 1 m m 1 FF 0 1 1 p n Internal source clock Counter m p m p n Shift registar Shift Shift Shift Shift Match detect Match detect One cycle period Match detect Match detect n m p n TC6CR TC6S TC6CR TFF6 PWREG6 Timer F F6 PWM6 pin INTTC6 interrupt request Write to PWREG6 Write to PWREG6 ...

Page 253: ...iately after programming of TTREGj Therefore if TTREGj is changed while the timer is running an expected operation may not be obtained Note 3 j 5 6 Figure 11 6 16 Bit Timer Mode Timing Chart TC5 and TC6 Table 11 6 Source Clock for 16 Bit Timer Mode Source Clock Resolution Maximum Time Setting NORMAL1 2 IDLE1 2 mode SLOW1 2 SLEEP1 2 mode fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK...

Page 254: ...eading data of PWREG6 and 5 is previous value until INTTC6 is generated For the pin used for PWM output the output latch of the I O port must be set to 1 Note 1 In the PWM mode program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt request is generated normally in the INTTC6 interrupt service routine If the programming of PWREGj and the interrupt request occur at the same t...

Page 255: ... 2 mode SLOW1 2 SLEEP1 2 mode fc 16 MHz fs 32 768 kHz fc 16 MHz fs 32 768 kHz DV7CK 0 DV7CK 1 fc 211 fs 23 Hz fs 23 Hz 128 µs 244 14 µs 8 39 s 16 s fc 27 fc 27 8 µs 524 3 ms fc 25 fc 25 2 µs 131 1 ms fc 23 fc 23 500 ns 32 8 ms fs fs fs 30 5 µs 30 5 µs 2 s 2 s fc 2 fc 2 125 ns 8 2 ms fc fc 62 5 ns 4 1 ms Example Generating a pulse with 1 ms high level width and a period of 32 768 ms fc 16 0 MHz Set...

Page 256: ...1 FFFF 0 bm cp b c 1 1 cp n a an Internal source clock 16 bit shift register Shift Shift Shift Shift Counter Match detect Match detect One cycle period Match detect Match detect an bm cp an m p TC6CR TC6S TC6CR TFF6 PWREG5 Lower byte Timer F F6 PWM6 pin INTTC6 interrupt request PWREG6 Upper byte Write to PWREG6 Write to PWREG6 Write to PWREG5 Write to PWREG5 ...

Page 257: ...ote 1 In the PPG mode do not change the PWREGi and TTREGi settings while the timer is running Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode the new values pro grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi Therefore if PWREGi and TTREGi are changed while the timer is running an expected operation may not be obtained ...

Page 258: ...1 1 mn mn 1 mn 1 0 qr 0 qr 1 0 Internal source clock Counter Write of 0 Match detect Match detect Match detect mn mn mn Match detect Match detect n m r q Held at the level when the timer stops F F clear TC6CR TC6S TC6CR TFF6 PWREG5 Lower byte Timer F F6 PPG6 pin INTTC6 interrupt request PWREG6 Upper byte TTREG5 Lower byte TTREG6 Upper byte ...

Page 259: ... timer register TTREG6 5 value is detected after the timer is started by setting TC6CR TC6S to 1 the counter is cleared by generating the INTTC6 interrupt request After stopping the timer in the INTTC6 interrupt service routine set SYSCR2 SYSCK to 1 to switch the system clock from the high frequency to low frequency and then clear of SYSCR2 XEN to 0 to stop the high frequency clock Table 11 8 Sett...

Page 260: ...frequency to high frequency and then SYSCR2 XTEN to 0 to stop the low frequency clock Table 11 9 Setting Time in High Frequency Warm Up Counter Mode Minimum time Setting TTREG6 5 0100H Maximum time Setting TTREG6 5 FF00H 16 µs 4 08 ms Example After checking high frequency clock oscillation stability with TC6 and 5 switching to the NORMAL1 mode SET SYSCR2 7 SYSCR2 XEN 1 LD TC5CR 63H Sets TFF5 0 sou...

Page 261: ... 2 UART control register 1 Transmit data buffer Receive data buffer fc 13 fc 26 fc 52 fc 104 fc 208 fc 416 fc 96 Stop bit Parity bit fc 26 fc 27 fc 28 Baud rate generator Transmit receive clock 2 4 3 2 2 2 Noise rejection circuit M P X Transmit control circuit Shift register Shift register Receive control circuit MPX Multiplexer UART1CR1 TD1BUF RD1BUF INTTXD1 INTRXD1 UART1SR UART1CR2 RXD1 TXD1 INT...

Page 262: ...6 fc s are always regarded as signals when UART1CR2 RXDNC 10 longer than 192 fc s and when UART1CR2 RXDNC 11 longer than 384 fc s UART1 Control Register1 UART1CR1 0F95H 7 6 5 4 3 2 1 0 TXE RXE STBT EVEN PE BRG Initial value 0000 0000 TXE Transfer operation 0 1 Disable Enable Write only RXE Receive operation 0 1 Disable Enable STBT Transmit stop bit length 0 1 1 bit 2 bits EVEN Even numbered parity...

Page 263: ... OERR Overrun error flag 0 1 No overrun error Overrun error RBFL Receive data buffer full flag 0 1 Receive data buffer empty Receive data buffer full TEND Transmit end flag 0 1 On transmitting Transmit end TBEP Transmit data buffer empty flag 0 1 Transmit data buffer full Transmit data writing is finished Transmit data buffer empty UART1 Receive Data Buffer RD1BUF 0F97H 7 6 5 4 3 2 1 0 Read only I...

Page 264: ...follows Figure 12 2 Transfer Data Format Figure 12 3 Caution on Changing Transfer Data Format Note In order to switch the transfer data format perform transmit operations in the above Figure 12 3 sequence except for the initial setting Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity St...

Page 265: ...arity bit are sampled at three times of RT7 RT8 and RT9 during one receiver clock interval RT clock RT0 is the position where the bit supposedly starts Bit is determined according to major ity rule The data are the same twice or more out of three samplings Figure 12 4 Data Sampling Method Table 12 1 Transfer Rate Example BRG Source Clock 16 MHz 8 MHz 4 MHz 000 76800 baud 38400 baud 19200 baud 001 ...

Page 266: ...data are written to TD1BUF the TXD1 pin is fixed at high level When transmitting data first read UART1SR then write data in TD1BUF Otherwise UART1SR TBEP is not zero cleared and transmit does not start 12 8 2 Data Receive Operation Set UART1CR1 RXE to 1 When data are received via the RXD1 pin the receive data are transferred to RD1BUF Receive data buffer At this time the data transmitted includes ...

Page 267: ...when the RD1BUF is read after reading the UART1SR Figure 12 6 Generation of Framing Error 12 9 3 Overrun Error When all bits in the next data are received while unread data are still in RD1BUF overrun error flag UART1SR OERR is set to 1 In this case the receive data is discarded data in RD1BUF are not affected The UART1SR OERR is cleared to 0 when the RD1BUF is read after reading the UART1SR Parit...

Page 268: ... reading the RD1BUF Therefore after reading the RD1BUF read the UART1SR again to check whether or not the overrun error flag which should have been cleared still remains set 12 9 5 Transmit Data Buffer Empty When no data is in the transmit buffer TD1BUF that is when data in TD1BUF are transferred to the transmit shift register and data transmit starts transmit data buffer empty flag UART1SR TBEP i...

Page 269: ...transmit is started after writing the TD1BUF Figure 12 10 Generation of Transmit End Flag and Transmit Data Buffer Empty Shift register Data write Data write zzzz xxxx yyyy Start Bit 0 Final bit Stop 1xxxx0 1 1xxxx 1x 1 1yyyy0 TD1BUF TXD1 pin UART1SR TBEP INTTXD1 interrupt After reading UART1SR writing TD1BUF clears TBEP Shift register 1yyyy 1xx 1x 1 Stop Start 1yyyy0 Bit 0 TXD1 pin UART1SR TBEP U...

Page 270: ...Page 148 12 Asynchronous Serial interface UART1 12 9 Status Flag T5CL8 ...

Page 271: ... 2 UART control register 1 Transmit data buffer Receive data buffer fc 13 fc 26 fc 52 fc 104 fc 208 fc 416 fc 96 Stop bit Parity bit fc 26 fc 27 fc 28 Baud rate generator Transmit receive clock 2 4 3 2 2 2 Noise rejection circuit M P X Transmit control circuit Shift register Shift register Receive control circuit MPX Multiplexer UART2CR1 TD2BUF RD2BUF INTTXD2 INTRXD2 UART2SR UART2CR2 RXD2 TXD2 INT...

Page 272: ...6 fc s are always regarded as signals when UART2CR2 RXDNC 10 longer than 192 fc s and when UART2CR2 RXDNC 11 longer than 384 fc s UART2 Control Register1 UART2CR1 0F98H 7 6 5 4 3 2 1 0 TXE RXE STBT EVEN PE BRG Initial value 0000 0000 TXE Transfer operation 0 1 Disable Enable Write only RXE Receive operation 0 1 Disable Enable STBT Transmit stop bit length 0 1 1 bit 2 bits EVEN Even numbered parity...

Page 273: ... OERR Overrun error flag 0 1 No overrun error Overrun error RBFL Receive data buffer full flag 0 1 Receive data buffer empty Receive data buffer full TEND Transmit end flag 0 1 On transmitting Transmit end TBEP Transmit data buffer empty flag 0 1 Transmit data buffer full Transmit data writing is finished Transmit data buffer empty UART2 Receive Data Buffer RD2BUF 0F9AH 7 6 5 4 3 2 1 0 Read only I...

Page 274: ...follows Figure 13 2 Transfer Data Format Figure 13 3 Caution on Changing Transfer Data Format Note In order to switch the transfer data format perform transmit operations in the above Figure 13 3 sequence except for the initial setting Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity St...

Page 275: ...arity bit are sampled at three times of RT7 RT8 and RT9 during one receiver clock interval RT clock RT0 is the position where the bit supposedly starts Bit is determined according to major ity rule The data are the same twice or more out of three samplings Figure 13 4 Data Sampling Method Table 13 1 Transfer Rate Example BRG Source Clock 16 MHz 8 MHz 4 MHz 000 76800 baud 38400 baud 19200 baud 001 ...

Page 276: ...data are written to TD2BUF the TXD2 pin is fixed at high level When transmitting data first read UART2SR then write data in TD2BUF Otherwise UART2SR TBEP is not zero cleared and transmit does not start 13 8 2 Data Receive Operation Set UART2CR1 RXE to 1 When data are received via the RXD2 pin the receive data are transferred to RD2BUF Receive data buffer At this time the data transmitted includes ...

Page 277: ...when the RD2BUF is read after reading the UART2SR Figure 13 6 Generation of Framing Error 13 9 3 Overrun Error When all bits in the next data are received while unread data are still in RD2BUF overrun error flag UART2SR OERR is set to 1 In this case the receive data is discarded data in RD2BUF are not affected The UART2SR OERR is cleared to 0 when the RD2BUF is read after reading the UART2SR Parit...

Page 278: ... reading the RD2BUF Therefore after reading the RD2BUF read the UART2SR again to check whether or not the overrun error flag which should have been cleared still remains set 13 9 5 Transmit Data Buffer Empty When no data is in the transmit buffer TD2BUF that is when data in TD2BUF are transferred to the transmit shift register and data transmit starts transmit data buffer empty flag UART2SR TBEP i...

Page 279: ...transmit is started after writing the TD2BUF Figure 13 10 Generation of Transmit End Flag and Transmit Data Buffer Empty Shift register Data write Data write zzzz xxxx yyyy Start Bit 0 Final bit Stop 1xxxx0 1 1xxxx 1x 1 1yyyy0 TD2BUF TXD2 pin UART2SR TBEP INTTXD2 interrupt After reading UART2SR writing TD2BUF clears TBEP Shift register 1yyyy 1xx 1x 1 Stop Start 1yyyy0 Bit 0 TXD2 pin UART2SR TBEP U...

Page 280: ...Page 158 13 Asynchronous Serial interface UART2 13 9 Status Flag T5CL8 ...

Page 281: ...terface SIO interrupt Internal clock input To BUS Shift register on transmitter Shift register on receiver Serial data output Control circuit Shift clock Internal data bus Port Note Serial data output Port Note Serial data input Port Note Note Set the register of port correctly for the port assigned as serial interface pins For details see the description of the input output port control register ...

Page 282: ...al Interface Control Register SIO1CR 0020H 7 6 5 4 3 2 1 0 SIOS SIOINH SIOM SIODIR SCK Initial value 0000 0000 SIOS Specify start stop of transfer 0 Stop 1 Start R W SIOINH Forcibly stops transfer Note 1 0 1 Forcibly stop Automatically cleared to 0 after stopping SIOM Selects transfer mode 00 Transmit mode 01 Receive mode 10 Transmit receive mode 11 Reserved SIODIR Selects direction of transfer 0 ...

Page 283: ...alue 0010 00 SIOF Serial transfer operation status monitor 0 Transfer finished 1 Transfer in progress Read only SEF Number of clocks monitor 0 8 clocks 1 1 to 7 clocks TXF Transmit buffer empty flag 0 Data exists in transmit buffer 1 No data exists in transmit buffer RXF Receive buffer full flag 0 No data exists in receive buffer 1 Data exists in receive buffer TXERR Transfer operation error flag ...

Page 284: ... or writing is completed shown in Figure 14 2 Automatic wait Function Example of transmit mode The maximum time from releasing the automatic wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from SCK1 pin Figure 14 2 Automatic wait Function Example of transmit mode Table 14 1 Serial Clock Rate fc 16 MHz fs 32 768kHz NORMAL1 2 IDLE1 ...

Page 285: ...ata is shifted on the leading edge of the serial clock falling edge of the SCK1 pin input output 2 Trailing edge shift Data is shifted on the trailing edge of the serial clock rising edge of the SCK1 pin input output Figure 14 4 Shift Edge tSCKL tSCKH tSCKL tSCKH 4 fc SCK1 pin 7 Bit7 Shift out 01234 012345 0123456 Bit5 Bit6 Bit5 Bit6 Bit7 67 567 a Leading edge shift Example of MSB transfer b Trail...

Page 286: ...SB transmit mode is selected by setting SIO1CR SIODIR to 0 in which case the data is transferred sequentially beginning with the most significant bit Bit7 2 LSB transmit mode LSB transmit mode is selected by setting SIO1CR SIODIR to 1 in which case the data is transferred sequentially beginning with the least significant bit Bit0 14 3 2 2 Receive mode 1 MSB receive mode MSB receive mode is selecte...

Page 287: ...K Transfer direction is selected by using SIO1CR SIODIR When a transmit data is written to the transmit buffer register SIO1TDB SIO1SR TXF is cleared to 0 After SIO1CR SIOS is set to 1 SIO1SR SIOF is set synchronously to 1 the falling edge of SCK1 pin The data is transferred sequentially starting from SO1 pin with the direction of the bit specified by SIO1CR SIODIR synchronizing with the SCK1 pin ...

Page 288: ...era tion is started Then INTSIO1 interrupt request is generated after SIO1SR TXERR is set to 1 3 Stopping the transmit operation There are two ways for stopping transmits operation The way of clearing SIO1CR SIOS When SIO1CR SIOS is cleared to 0 transmit operation is stopped after all transfer of the data is finished When transmit operation is finished SIO1SR SIOF is cleared to 0 and SO1 pin is ke...

Page 289: ...is set to 1 SIO1SR TXERR is set to 1 immediately after shift operation is started and then INTSIO1 interrupt request is generated SIO1 pin is kept in high level when SIO1SR TXERR is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO1CR SIOINH to 1 In this case SIO1CR SIOS SIO1SR register SIO1RDB register and SIO1TDB register are initialized Writing transmit...

Page 290: ...t request is generated and SIO1SR RXF is set to 1 Note In internal clock operation when the SIO1CR SIOS is set to 1 the serial clock is generated from SCK1 pin after maximum 1 cycle of serial clock frequency 2 During the receive operation The SIO1SR RXF is cleared to 0 by reading a data from SIO1RDB In the internal clock operation the serial clock stops to H level by an automatic wait function whe...

Page 291: ...operation SIO1CR SIOS must be cleared to 0 before SIO1SR SEF is set to 1 by starting the next shift operation The way of setting SIO1CR SIOINH Receive operation is stopped immediately after SIO1CR SIOINH is set to 1 In this case SIO1CR SIOS SIO1SR register SIO1RDB register and SIO1TDB register are initialized Figure 14 10 Example of Internal Clock and MSB Receive Mode A6 A5 A4 A3 A2 A1 A0 A7 B7 B6...

Page 292: ...ding the SIO1RDB again When SIO1SR RXERR is cleared to 0 after reading the received data SIO1SR RXF is cleared to 0 After clearing SIO1CR SIOS to 0 when 8 bit serial clock is input to SCK1 pin receive operation is stopped To restart the receive operation confirm that SIO1SR SIOF is cleared to 0 If the receive error occurs set the SIO1CR SIOINH to 1 for stopping the receive opera tion immediately I...

Page 293: ...el between the first clock falling edge of SCK1 pin and eighth clock falling edge SIO1SR TXF is set to 1 at the rising edge of SCK1 pin after the data written to the SIO1TDB is transferred to shift register When 8 bit data has been received the received data is transferred to SIO1RDB from shift register then the INTSIO1 interrupt request occurs synchronizing with setting SIO1SR RXF to 1 Note 1 In ...

Page 294: ...ing the next data to SIO1TDB must be finished before the shift operation of the next data begins If the transmit data is not written to SIO1TDB after SIO1SR TXF is set to 1 transmit error occurs immediately after shift operation is started When the transmit error occurred SIO1SR TXERR is set to 1 If received data is not read out from SIO1RDB before next shift operation starts after setting SIO1SR ...

Page 295: ...on Start shift operation Start shift operation Writing transmit data A Writing transmit data B D6 D5 D4 D3 D2 D1 D0 D7 E7 E6 E5 E4 E3 E2 E1 F7 E0 F6 F5 F4 F3 F2 F1 F0 Clearing SIOS Writing transmit data C E D F Reading received data D Reading received data E Reading received data F SIO1CR SIOS SIO1SR SIOF SIO1SR SEF SCK1 pin output SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR TXF SIO1SR RXF SI...

Page 296: ...mmediately after starting shift operation And INTSIO1 interrupt request is generated after all of the 8 bit data has been received SO1 pin is kept in high level when SIO1SR TXERR is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO1CR SIOINH to 1 after the received data is read from SIO1RDB In this case SIO1CR SIOS SIO1SR register SIO1RDB register and SIO1...

Page 297: ... RXF is cleared to 0 After clearing SIO1CR SIOS to 0 when 8 bit serial clock is input to SCK1 pin re ceive operation is stopped To restart the receive operation confirm that SIO1SR SIOF is cleared to 0 If the received error occurs set the SIO1CR SIOINH to 1 for stopping the receive operation immediately In this case SIO1CR SIOS SIO1SR register SIO1RDB reg ister and SIO1TDB register are initialized...

Page 298: ...ng transmit data B Writing transmit data A Unknown C B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Reading received data E Reading received data D OOH E D SIO1CR SIOS SIO1SR SIOF SIO1SR SEF SCK1 pin output SO1 pin SI1 pin INTSIO1 interrupt r...

Page 299: ...terface SIO interrupt Internal clock input To BUS Shift register on transmitter Shift register on receiver Serial data output Control circuit Shift clock Internal data bus Port Note Serial data output Port Note Serial data input Port Note Note Set the register of port correctly for the port assigned as serial interface pins For details see the description of the input output port control register ...

Page 300: ...al Interface Control Register SIO2CR 0031H 7 6 5 4 3 2 1 0 SIOS SIOINH SIOM SIODIR SCK Initial value 0000 0000 SIOS Specify start stop of transfer 0 Stop 1 Start R W SIOINH Forcibly stops transfer Note 1 0 1 Forcibly stop Automatically cleared to 0 after stopping SIOM Selects transfer mode 00 Transmit mode 01 Receive mode 10 Transmit receive mode 11 Reserved SIODIR Selects direction of transfer 0 ...

Page 301: ...alue 0010 00 SIOF Serial transfer operation status monitor 0 Transfer finished 1 Transfer in progress Read only SEF Number of clocks monitor 0 8 clocks 1 1 to 7 clocks TXF Transmit buffer empty flag 0 Data exists in transmit buffer 1 No data exists in transmit buffer RXF Receive buffer full flag 0 No data exists in receive buffer 1 Data exists in receive buffer TXERR Transfer operation error flag ...

Page 302: ... or writing is completed shown in Figure 15 2 Automatic wait Function Example of transmit mode The maximum time from releasing the automatic wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from SCK2 pin Figure 15 2 Automatic wait Function Example of transmit mode Table 15 1 Serial Clock Rate fc 16 MHz fs 32 768kHz NORMAL1 2 IDLE1 ...

Page 303: ...ata is shifted on the leading edge of the serial clock falling edge of the SCK2 pin input output 2 Trailing edge shift Data is shifted on the trailing edge of the serial clock rising edge of the SCK2 pin input output Figure 15 4 Shift Edge tSCKL tSCKH tSCKL tSCKH 4 fc SCK2 pin 7 Bit7 Shift out 01234 012345 0123456 Bit5 Bit6 Bit5 Bit6 Bit7 67 567 a Leading edge shift Example of MSB transfer b Trail...

Page 304: ...B transmit mode is selected by setting SIO2CR SIODIR to 0 in which case the data is transferred sequentially beginning with the most significant bit Bit7 2 LSB transmit mode LSB transmit mode is selected by setting SIO2CR SIODIR to 1 in which case the data is transferred sequentially beginning with the least significant bit Bit0 15 3 2 2 Receive mode 1 MSB receive mode MSB receive mode is selected...

Page 305: ...K Transfer direction is selected by using SIO2CR SIODIR When a transmit data is written to the transmit buffer register SIO2TDB SIO2SR TXF is cleared to 0 After SIO2CR SIOS is set to 1 SIO2SR SIOF is set synchronously to 1 the falling edge of SCK2 pin The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by SIO2CR SIODIR synchronizing with the SCK2 pin ...

Page 306: ...era tion is started Then INTSIO2 interrupt request is generated after SIO2SR TXERR is set to 1 3 Stopping the transmit operation There are two ways for stopping transmits operation The way of clearing SIO2CR SIOS When SIO2CR SIOS is cleared to 0 transmit operation is stopped after all transfer of the data is finished When transmit operation is finished SIO2SR SIOF is cleared to 0 and SO2 pin is ke...

Page 307: ...is set to 1 SIO2SR TXERR is set to 1 immediately after shift operation is started and then INTSIO2 interrupt request is generated SIO2 pin is kept in high level when SIO2SR TXERR is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO2CR SIOINH to 1 In this case SIO2CR SIOS SIO2SR register SIO2RDB register and SIO2TDB register are initialized Writing transmit...

Page 308: ...t request is generated and SIO2SR RXF is set to 1 Note In internal clock operation when the SIO2CR SIOS is set to 1 the serial clock is generated from SCK2 pin after maximum 1 cycle of serial clock frequency 2 During the receive operation The SIO2SR RXF is cleared to 0 by reading a data from SIO2RDB In the internal clock operation the serial clock stops to H level by an automatic wait function whe...

Page 309: ...operation SIO2CR SIOS must be cleared to 0 before SIO2SR SEF is set to 1 by starting the next shift operation The way of setting SIO2CR SIOINH Receive operation is stopped immediately after SIO2CR SIOINH is set to 1 In this case SIO2CR SIOS SIO2SR register SIO2RDB register and SIO2TDB register are initialized Figure 15 10 Example of Internal Clock and MSB Receive Mode A6 A5 A4 A3 A2 A1 A0 A7 B7 B6...

Page 310: ...ding the SIO2RDB again When SIO2SR RXERR is cleared to 0 after reading the received data SIO2SR RXF is cleared to 0 After clearing SIO2CR SIOS to 0 when 8 bit serial clock is input to SCK2 pin receive operation is stopped To restart the receive operation confirm that SIO2SR SIOF is cleared to 0 If the receive error occurs set the SIO2CR SIOINH to 1 for stopping the receive opera tion immediately I...

Page 311: ...el between the first clock falling edge of SCK2 pin and eighth clock falling edge SIO2SR TXF is set to 1 at the rising edge of SCK2 pin after the data written to the SIO2TDB is transferred to shift register When 8 bit data has been received the received data is transferred to SIO2RDB from shift register then the INTSIO2 interrupt request occurs synchronizing with setting SIO2SR RXF to 1 Note 1 In ...

Page 312: ...ing the next data to SIO2TDB must be finished before the shift operation of the next data begins If the transmit data is not written to SIO2TDB after SIO2SR TXF is set to 1 transmit error occurs immediately after shift operation is started When the transmit error occurred SIO2SR TXERR is set to 1 If received data is not read out from SIO2RDB before next shift operation starts after setting SIO2SR ...

Page 313: ...on Start shift operation Start shift operation Writing transmit data A Writing transmit data B D6 D5 D4 D3 D2 D1 D0 D7 E7 E6 E5 E4 E3 E2 E1 F7 E0 F6 F5 F4 F3 F2 F1 F0 Clearing SIOS Writing transmit data C E D F Reading received data D Reading received data E Reading received data F SIO2CR SIOS SIO2SR SIOF SIO2SR SEF SCK2 pin output SO2 pin SI2 pin INTSIO2 interrupt request SIO2SR TXF SIO2SR RXF SI...

Page 314: ...mmediately after starting shift operation And INTSIO2 interrupt request is generated after all of the 8 bit data has been received SO2 pin is kept in high level when SIO2SR TXERR is set to 1 When transmit error occurs transmit operation must be forcibly stop by writing SIO2CR SIOINH to 1 after the received data is read from SIO2RDB In this case SIO2CR SIOS SIO2SR register SIO2RDB register and SIO2...

Page 315: ... RXF is cleared to 0 After clearing SIO2CR SIOS to 0 when 8 bit serial clock is input to SCK2 pin re ceive operation is stopped To restart the receive operation confirm that SIO2SR SIOF is cleared to 0 If the received error occurs set the SIO2CR SIOINH to 1 for stopping the receive operation immediately In this case SIO2CR SIOS SIO2SR register SIO2RDB reg ister and SIO2TDB register are initialized...

Page 316: ...ng transmit data B Writing transmit data A Unknown C B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Reading received data E Reading received data D OOH E D SIO2CR SIOS SIO2SR SIOF SIO2SR SEF SCK2 pin output SO2 pin SI2 pin INTSIO2 interrupt r...

Page 317: ... registers are used for control the serial bus interface and monitor the operation status Serial bus interface control register A SBICRA Serial bus interface control register B SBICRB Serial bus interface data buffer register SBIDBR I2 C bus address register I2CAR Serial bus interface status register A SBISRA Serial bus interface status register B SBISRB 16 3 Software Reset A serial bus interface ...

Page 318: ...8 bits 1 1 S A C K A C K A C K P Slave address Data Data 1 to 8 bits 1 R W 8 bits 1 1 1 or more 1 or more 1 to 8 bits 1 1 1 S A C K A C K A C K P Slave address Data Data Slave address 1 to 8 bits 1 R W 8 bits A C K R W 8 bits 1 1 or more 1 to 8 bits 1 1 S A C K A C K A C K P S Data Data Data 1 to 8 bits 1 a Addressing format b Addressing format with restart c Free data format S R W ACK P Start con...

Page 319: ... 0 BC ACK SCK Initial value 0000 000 BC Number of transferred bits BC ACK 0 ACK 1 Write only Number of Clock Bits Number of Clock Bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 ACK Acknowledgement mode specification ACK Master mode Slave mode R W 0 Not generate a clock pulse for an acknowledgement Not count a clock pulse for an acknowledgement ...

Page 320: ...e address ALS Initial value 0000 0000 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA Slave address selection Write only ALS Address recognition mode spec ification 0 Slave address recognition 1 Non slave address recognition Serial Bus Interface Control Register B SBICRB 0F93H 7 6 5 4 3 2 1 0 MST TRX BB PIN SBIM SWRST1 SWRST0 Initial value 0001 0000 MST Master slave selection 0 Slave Write only 1 Master TRX Transm...

Page 321: ...ss or the detection of GENERAL CALL The Table 16 1 shows the SCL and SDA pins status in acknowledgment mode 16 5 1 2 Non acknowledgment mode ACK 0 To set the device as a non acknowledgement mode the ACK Bit4 in SBICRA should be cleared to 0 MST Master slave selection status monitor 0 Slave Read only 1 Master TRX Transmitter receiver selection status monitor 0 Receiver 1 Transmitter BB Bus status m...

Page 322: ...cy output from the SCL pin in the master mode Four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from SCL pin Note Since the serial bus interface can not be used as the fast mode and the high speed mode do not set SCK as the frequency that is over 100 kHz Figure 16 3 Clock Source 16 5 3 2 Clock synchronization In the I2 C bus i...

Page 323: ...s recognition mode specification When the serial bus interface circuit is used with an addressing format to recognize the slave address clear the ALS Bit0 in I2CAR to 0 and set the SA Bits7 to 1 in I2CAR to the slave address When the serial bus interface circuit is used with a free data format not to recognize the slave address set the ALS to 1 With a free data format the slave address and the dir...

Page 324: ...X and PIN and 0 to the BB Do not modify the contents of MST TRX BB and PIN until a stop condition is gener ated on a bus When a stop condition is generated and the SCL line on a bus is pulled down to low level by another device a stop condition is generated after releasing the SCL line Figure 16 6 Stop Condition Generation The bus condition can be indicated by reading the contents of the BB Bit5 i...

Page 325: ...er confirming that a bus is free 16 5 10Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus a bus arbitration procedure is imple mented in order to guarantee the contents of transferred data Data on the SDA line is used for bus arbitration of the I2C bus The following shows an example of a bus arbitration procedure when two master devices exist si...

Page 326: ...tes in the free data format ALS 1 the AAS is set to 1 after receiving the first 1 word of data The AAS is cleared to 0 by writing data to the SBIDBR or reading data from the SBIDBR 16 5 12GENERAL CALL detection monitor The AD0 Bit1 in SBISRB is set to 1 when all 8 bit received data is 0 immediately after a start condi tion in a slave mode The AD0 is cleared to 0 when a start or stop condition is d...

Page 327: ...to the SBIDBR are output The time from generating the START condition until the falling SCL pin takes tLOW An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle and the PIN is cleared to 0 The SCL pin is pulled down to the low level while the PIN is 0 When an interrupt request occurs the TRX changes by the hardware according to the direction bit only when an acknowledge s...

Page 328: ...more than one word in length repeat the procedure from the LRB test above Figure 16 10 Example of when BC 000 ACK 1 2 When the TRX is 0 Receiver mode When the next transmitted data is other than of 8 bits set the BC again Set the ACK to 1 and read the received data from the SBIDBR Reading data is undefined immediately after a slave address is sent After the data is read the PIN becomes 1 A serial ...

Page 329: ... GENERAL CALL is received At the end of transferring or receiving after matching of slave address or receiving of GENERAL CALL A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode And an INTSBI interrupt request occurs when word data transfer terminates after losing arbitration The behavior of INTSBI interrupt request and PIN after losing arbitration are...

Page 330: ...SBIDBR 0 1 0 In the slave receiver mode a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is 1 0 0 In the slave transmitter mode 1 word data is transmitted Test the LRB If the LRB is set to 1 set the PIN to 1 since the receiver does not request next data Then clear the TRX to 0 to release the bus If the LRB is set to 0 set the numb...

Page 331: ...ee state generate a start condition with proce dure 16 6 2 Start condition and slave address generation In order to meet setup time when restarting take at least 4 7 µs of waiting time by software from the time of restarting to confirm that a bus is free until the time to generate a start condition Note When the master is in the receiver mode it is necessary to stop the data transmission from the ...

Page 332: ...Page 210 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 ...

Page 333: ...essive comparison circuit Note Before using AD converter set appropriate value to I O port register conbining a analog input port For details see the sec tion on I O ports Figure 17 1 10 bit AD Converter 2 4 10 8 AINDS ADRS R 2 R 2 R ACK AMD IREFON AD conversion result register 1 2 AD converter control register 1 2 ADBF EOCF INTADC SAIN n Successive approximate circuit ADCCR2 ADCDR1 ADCDR2 ADCCR1 ...

Page 334: ... pins because analog input port use as general input port And for port near to analog input Do not input intense signaling of change Note 4 The ADCCR1 ADRS is automatically cleared to 0 after starting conversion Note 5 Do not set ADCCR1 ADRS newly again during AD conversion Before setting ADCCR1 ADRS newly again check ADCDR2 EOCF to see that the conversion is completed or wait until the interrupt ...

Page 335: ...ntrol 0 1 Connected only during AD conversion Always connected R W ACK AD conversion time select Refer to the following table about the con version time 000 001 010 011 100 101 110 111 39 fc Reserved 78 fc 156 fc 312 fc 624 fc 1248 fc Reserved Table 17 1 ACK setting and Conversion time Condition Conversion time 16 MHz 8 MHz 4 MHz 2 MHz 10 MHz 5 MHz 2 5 MHz ACK 000 39 fc 19 5 µs 15 6 µs 001 Reserve...

Page 336: ...2 The ADCDR2 ADBF is set to 1 when AD conversion starts and cleared to 0 when AD conversion finished It also is cleared upon entering STOP mode or SLOW mode Note 3 If a read instruction is executed for ADCDR2 read data of bit3 to bit0 are unstable EOCF AD conversion end flag 0 1 Before or during conversion Conversion completed Read only ADBF AD conversion BUSY flag 0 1 During stop of AD conversion...

Page 337: ... voltage at the analog input pin specified by ADCCR1 SAIN is performed repeatedly In this mode AD conversion is started by setting ADCCR1 ADRS to 1 after setting ADCCR1 AMD to 11 Repeat mode After completion of the AD conversion the conversion result is stored in AD converted value registers ADCDR1 ADCDR2 and at the same time ADCDR2 EOCF is set to 1 the AD conversion finished inter rupt INTADC is ...

Page 338: ...y 4 After an elapse of the specified AD conversion time the AD converted value is stored in AD con verted value register 1 ADCDR1 and the AD conversion finished flag EOCF of AD converted value register 2 ADCDR2 is set to 1 upon which time AD conversion interrupt INTADC is gener ated 5 EOCF is cleared to 0 by a read of the conversion result However if reconverted before a register read although EOC...

Page 339: ...nalog reference voltage is automatically disconnected there is no possibility of current flowing into the analog reference voltage Example After selecting the conversion time 19 5 µs at 16 MHz and the analog input channel AIN3 pin perform AD con version once After checking EOCF read the converted value store the lower 2 bits in address 0009EH nd store the upper 8 bits in address 0009FH in RAM The ...

Page 340: ...tage and AD Conversion Result The analog input voltage is corresponded to the 10 bit digital value converted by the AD as shown in Figure 17 4 Figure 17 4 Analog Input Voltage and AD Conversion Result Typ 1 0 01H 02H 03H 3FDH 3FEH 3FFH 2 3 1021 1022 1023 1024 Analog input voltage 1024 AD conversion result VAREF VSS ...

Page 341: ... we recommend that the AD conversion end interrupt processing rou tine be called after checking whether or not an interrupt request with priority higher than INTADC has been set 17 6 2 Analog input pin voltage range Make sure the analog input pins AIN0 to AIN15 are used at voltages within VAREF to VSS If any voltage outside this range is applied to one of the analog input pins the converted value ...

Page 342: ...Page 220 17 10 bit AD Converter ADC 17 6 Precautions about AD Converter T5CL8 ...

Page 343: ...onding I O pins to input mode by I O port register beforehand 18 3 Function Stop mode can be entered by setting up the System Control Register SYSCR1 and can be exited by detecting the L level on STOP0 to STOP3 pins which are enabled by STOPCR for releasing STOP mode Note1 Key on Wakeup Control Register STOPCR 7 6 5 4 3 2 1 0 0F9FH STOP3 STOP2 STOP1 STOP0 Initial value 0000 STOP3 STOP mode release...

Page 344: ...y be different from a value which is detected by Key on Wakeup input Figure 18 2 Note 4 STOP pin doesn t have the control register such as STOPCR so when STOP mode is released by STOP0 to STOP3 pins STOP pin also should be used as STOP mode release function Note 5 In STOP mode Key on Wakeup pin which is enabled as input mode for releasing STOP mode by Key on Wakeup Control Register STOPCR may gene...

Page 345: ...f pins T5CL8 in the serial PROM mode supports on board programming which enables users to program flash memory after the microcontroller is mounted on a user board Parallel PROM mode The parallel PROM mode allows the flash memory to be accessed as a stand alone flash memory by the program writer provided by the third party High speed access to the flash memory is available by control ling address ...

Page 346: ...hould be set to 1100B except when the flash memory needs to be written or erased 19 1 2 Flash Memory Bank Select Control FLSCR BANKSEL In the serial PROM mode a 2 kbyte BOOTROM is mapped to addresses 7800H 7FFFH and the flash mem ory is mapped to 2 banks at 8000H FFFFH Flash memory addresses 1000H 7FFFH are mapped to 9000H FFFFH as BANK0 and flash memory addresses 8000H FFFFH are mapped to 8000H F...

Page 347: ...writing data 19 2 2 Sector Erase 4 kbyte Erase This command erases the flash memory in units of 4 kbytes The flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address For example in the MCU mode to erase 4 kbytes from 7000H to 7FFFH specify one of the addresses in 7000H 7FFFH as the 6th bus write cycle In the serial PROM mode to erase 4 kbytes from 7000H to...

Page 348: ...D the flash ID and the security program status can be read from the flash memory Note The value at address F002H flash size depends on the size of flash memory incorporated in each product For example if the product has 60 kbyte flash memory 0EH is read from address F002H 19 2 5 Product ID Exit This command is used to exit the Product ID mode 19 2 6 Security Program This command enables the read p...

Page 349: ...the data toggling between 0 and 1 19 3 Toggle Bit D6 After the byte program chip erase and security program command sequence is executed any consecutive attempts to read from the same address is reversed bit 6 D6 of the data toggling between 0 and 1 until the opera tion is completed Therefore this toggle bit provides a software mechanism to check the completion of each opera tion Usually perform r...

Page 350: ...rial PROM Mode To access to the flash memory by using peripheral functions in the serial PROM mode run the RAM loader command to execute the control program in the RAM area The procedures to execute the control program in the RAM area is shown in 19 4 1 1 How to write to the flash memory by executing the control program in the RAM area in the RAM loader mode within the serial PROM mode 19 4 1 1 Ho...

Page 351: ...e LD IX 80H 3rd bus write cycle LD IX 0AAH 4th bus write cycle LD IY 55H 5th bus write cycle LD IX 10H 6th bus write cycle sLOOP1 LD W HL CMP W HL JR NZ sLOOP1 Loop until the same value is read SET FLSCR 3 Set BANK1 Flash Memory Write Process LD IX 0AAH 1st bus write cycle LD IY 55H 2nd bus write cycle LD IX 0A0H 3rd bus write cycle LD HL 3FH 4th bus write cycle F000H 3FH sLOOP2 LD W HL CMP W HL J...

Page 352: ...FLSMD to 0011B to enable command sequence execution 6 Execute the erase command sequence 7 Read the same flash memory address twice Repeat step 7 until the same data is read by two consecutive read operations 8 Execute the write command sequence It is not required to specify the bank to be written 9 Read the same flash memory address twice Repeat step 9 until the same data is read by two consecuti...

Page 353: ...4th bus write cycle LD IY 55H 5th bus write cycle LD HL 30H 6th bus write cycle sLOOP1 LD W HL CMP W HL JR NZ sLOOP1 Loop until the same value is read Flash Memory Write Process LD IX 0AAH 1st bus write cycle LD IY 55H 2nd bus write cycle LD IX 0A0H 3rd bus write cycle LD HL 3FH 4th bus write cycle 1000H 3FH sLOOP2 LD W HL CMP W HL JR NZ sLOOP2 Loop until the same value is read LD FLSCR 11001000B ...

Page 354: ...Page 232 19 Flash Memory 19 4 Access to the Flash Memory Area T5CL8 ...

Page 355: ...d MCU mode In the serial PROM mode the BOOTROM Mask ROM is mapped in addresses from 7800H to 7FFFH The flash memory is divided into two banks for mapping Therefore when the RAM loader mode 60H is used it is required to specify the flash memory address according to Figure 20 1 For detail of banks and control register refer to the chapter of Flash Memory Control Register Figure 20 1 Memory Address M...

Page 356: ...be careful no to affect these communication control pins Note 2 Operating range of high frequency in serial PROM mode is 2 MHz to 16 MHz Table 20 2 Serial PROM Mode Setting Pin Setting TEST pin High BOOT RXD1 pin High RESET pin Table 20 3 Pin Function in the Serial PROM Mode Pin Name Serial PROM Mode Input Output Function Pin Name MCU Mode TXD1 Output Serial data output Note 1 P02 BOOT RXD1 Input ...

Page 357: ...ins by a jumper or switch Note 2 When the reset control circuit on the application board effects activation of the serial PROM mode isolate the pin by a jumper or switch Note 3 For connection of other pins refer to Table 20 3 Pin Function in the Serial PROM Mode VDD 4 5 V to 5 5 V Serial PROM mode MCU mode VDD TEST RESET External control pull up XIN XOUT VSS GND BOOT RXD1 P01 TXD1 P02 T5CL8 VDD 4 ...

Page 358: ... pin to low 3 Set the TEST pin and BOOT RXD1 pins to high 4 Wait until the power supply and clock oscillation stabilize 5 Set the RESET pin to high 6 Input the matching data 5AH to the BOOT RXD1 pin after setup sequence For details of the setup timing refer to 20 15 UART Timing Figure 20 4 Serial PROM Mode Timing VDD TEST Input RESET Input PROGRAM Setup time for serial PROM mode Rxsup High level s...

Page 359: ...ating frequency of the microcontroller The baud rate can be modified by transmitting the baud rate modification data shown in Table 1 4 to T5CL8 The Table 20 5 shows an operating frequency and baud rate The frequencies which are not described in Table 20 5 can not be used Baud rate Default 9600 bps Data length 8 bits Parity addition None Stop bit 1 bit Table 20 4 Baud Rate Modification Data Baud r...

Page 360: ...aud Rate bps 76800 62500 57600 38400 31250 19200 9600 Baud Rate Modification Data 04H 05H 06H 07H 0AH 18H 28H Ref Fre quency MHz Rating MHz Baud rate bps bps bps bps bps bps bps 1 2 1 91 to 2 10 9615 0 16 2 4 3 82 to 4 19 31250 0 00 19231 0 16 9615 0 16 4 19 3 82 to 4 19 32734 4 75 20144 4 92 10072 4 92 3 4 9152 4 70 to 5 16 38400 0 00 19200 0 00 9600 0 00 5 4 70 to 5 16 39063 1 73 19531 1 73 9766...

Page 361: ...en the transfer is completed normally the RAM loader calculates the checksum After transmit ting the results the RAM loader jumps to the RAM address specified with the first data record in order to execute the user program When the security program is enabled the RAM loader mode is not activated In this case perform the chip erase beforehand in the flash memory erasing mode Before activating the R...

Page 362: ...de The external controller reads this code to recognize the flash memory status 7 Flash memory security program setting mode This mode disables reading and writing the flash memory data in parallel PROM mode In the serial PROM mode the flash memory writing and RAM loader modes are disabled To disable the flash memory security program perform the chip erase in the flash memory erasing mode ...

Page 363: ...9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error No data transmitted 3rd byte 4th byte Baud rate change data Table 20 4 9600 bps 9600 bps OK Echo back data Error A1H 3 A3H 3 62H 3 Note 1 5th byte 6th byte Operation command data F0H Modified baud rate Modified baud rate OK Echo back data F0H Error A1H 3 A3H 3 63H 3 Note 1 7th byte 8th byte Password count storage address ...

Page 364: ...n the flash memory writing mode In the case of a blank product do not transmit a password string Do not transmit a dummy password string 5 The n th 2 byte contains the erasure area specification data The upper 4 bits and lower 4 bits specify the start address and end address of the erasure area respectively For the detailed description see 1 13 Specifying the Erasure Area 6 The n th 1 byte and n t...

Page 365: ...5CL8 by the RESET pin and reactivate the serial PROM mode Table 20 8 Flash Memory Writing Mode Process Transfer Byte Transfer Data from External Controller to T5CL8 Baud Rate Transfer Data from T5CL8 to External Controller BOOT ROM 1st byte 2nd byte Matching data 5Ah 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error Nothing transmitted 3rd byte 4th byte Baud rate modific...

Page 366: ...ot send any data and enters the halt condition 8 The 9th byte contains the data for 7 to 0 bits of the password count storage address When the data received with the 9th byte has no receiving error the device does not send any data If a receiving error or password error occurs the device does not send any data and enters the halt condition 9 The 11th byte contains the data for 15 to 8 bits of the ...

Page 367: ... next operation command data Note 1 Do not write only the address from FFE0H to FFFFH when all flash memory data is the same If only these area are written the subsequent operation can not be executed due to password error Note 2 To rewrite data to Flash memory addresses at which data including FFH is already written make sure to erase the existing data by sector erase or chip erase before rewriti...

Page 368: ... reactivate the serial PROM mode Table 20 9 RAM Loader Mode Process Transfer Bytes Transfer Data from External Control ler to T5CL8 Baud Rate Transfer Data from T5CL8 to External Controller BOOT ROM 1st byte 2nd byte Matching data 5AH 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error Nothing transmitted 3rd byte 4th byte Baud rate modification data See Table 20 4 9600 bp...

Page 369: ...ice starts data record reception Therefore the received data except 3AH is ignored until the start mark is received After receiving the start mark the device receives the data record that consists of data length address record type write data and checksum The writing data of the data record is written into RAM specified by address Since the device starts checksum calculation after receiving an end...

Page 370: ...ers the halt condition after transmitting 3 bytes of operation command error code 63H 4 The 7th and the 8th bytes contain the upper and lower bits of the checksum respectively For how to calculate the checksum refer to 20 8 Checksum SUM 5 After sending the checksum the device waits for the next operation command data Table 20 10 Flash Memory SUM Output Process Transfer Bytes Transfer Data from Ext...

Page 371: ...ansfer Data from T5CL8 to External Controller BOOT ROM 1st byte 2nd byte Matching data 5AH 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error Nothing transmitted 3rd byte 4th byte Baud rate modification data See Table 20 4 9600 bps 9600 bps OK Echo back data Error A1H 3 A3H 3 62H 3 Note 1 5th byte 6th byte Operation command data C0H Modified baud rate Modified baud rate O...

Page 372: ...Page 250 20 Serial PROM Mode 20 6 Operation Mode T5CL8 5 After sending the checksum the device waits for the next operation command data ...

Page 373: ...the status code refer to 20 12 Flash Memory Status Code 5 After sending the status code the device waits for the next operation command data Table 20 12 Flash Memory Status Output Mode Process Transfer Bytes Transfer Data from External Con troller to T5CL8 Baud Rate Transfer Data from T5CL8 to External Controller BOOT ROM 1st byte 2nd byte Matching data 5AH 9600 bps 9600 bps Automatic baud rate ad...

Page 374: ... of the received data in Table 20 13 Flash Memory security program Setting Mode Process Transfer Bytes Transfer Data from External Con troller to T5CL8 Baud Rate Transfer Data from T5CL8 to External Controller BOOT ROM 1st byte 2nd byte Matching data 5AH 9600 bps 9600 bps Automatic baud rate adjustment OK Echo back data 5AH Error Nothing transmitted 3rd byte 4th byte Baud rate modification data Se...

Page 375: ...ition after transmitting 3 bytes of operation command error code 63H 4 The 7th through m th bytes of the transmitted and received data contain the same data as in the flash memory writing mode 5 The n th byte contains the status to be transmitted to the external controller in the case of the success ful security program ...

Page 376: ...unit and the calculated result is returned as a word Example The checksum which is transmitted by executing the flash memory write command RAM loader command or flash memory SUM output command is calculated in the manner as shown above Table 20 14 Error Code Transmit Data Meaning of Error Data 62H 62H 62H Baud rate modification error 63H 63H 63H Operation command error A1H A1H A1H Framing error in...

Page 377: ...mode RAM data written in the first received RAM address through the last received RAM address The length of data address record type and checksum in Intel Hex format are not included in the checksum Product ID Code Output mode 9th through 18th bytes of the transferred data For details refer to 20 11 Product ID Code Flash Memory Status Output mode 9th through 12th bytes of the transferred data For ...

Page 378: ...k product Even in this case the password count storage addresses and password comparison start address must be specified Table 20 16 shows the password setting in the blank product and non blank product Note 1 When addresses from FFE0H through FFFFH are filled with FFH the product is recognized as a blank product Note 2 The data including the same consecutive data three or more bytes can not be us...

Page 379: ...Program Development If a program is modified many times in the development stage confusion may arise as to the password Therefore it is recommended to use a fixed password in the program development stage Example Specify PNSA to F000H and the password string to 8 bytes from address F001H PCSA becomes F001H Password Section code abs 0F000H DB 08H PNSA definition DB CODE1234 Password string definiti...

Page 380: ...erved data 1DH 5th Reserved data 00H 6th Reserved data 00H 7th Reserved data 00H 8th ROM block count 01H 9th The first address of ROM Upper byte 10H 10th The first address of ROM Lower byte 00H 11th The end address of ROM Upper byte FFH 12th The end address of ROM Lower byte FFH 13th Checksum of the transferred data 2 s compliment for the sum of 3rd through 12th bytes D2H Table 20 18 Flash Memory ...

Page 381: ...ller T5CL8 stops UART communication and enters the halt condition RPENA Flash memory security program status 0 1 Security program is disabled Security program is enabled BLANK The status from FFE0H to FFFFH 0 1 All data is FFH in the area from FFE0H to FFFFH The value except FFH is included in the area from FFE0H to FFFFH RPENA BLANK Flash Memory Writing Mode RAM Loader Mode Flash memory SUM Outpu...

Page 382: ... the chip erase not sector erase to disable the security program Note When the sector erase is executed for the area containing no flash cell T5CL8 stops the UART commu nication and enters the halt condition Erasure Area Specification Data n 2 byte data 7 6 5 4 3 2 1 0 ERASTA ERAEND ERASTA The start address of the erasure area 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1...

Page 383: ... memory erasing mode Transmit UART data Transmit data F0H Infinite loop NG Chip erase Erase on entire area Transmit UART data Checksum of an entire area Receive data FAH Security Program setting mode Transmit UART data Transmit data FAH Security Program setting Security Program check Blank product check Infinite loop NG Blank product check Blank product check Non blank product Non blank product OK...

Page 384: ...ory in 4 kbyte units CEsec 15 ms 15 ms Table 20 20 UART Timing 2 VDD 4 5 to 5 5 V fc 2 to 16 MHz Topr 10 to 40 C Parameter Symbol Clock Frequency fc Minimum Required Time At fc 2 MHz At fc 16 MHz Time from the reset release to the acceptance of start bit of RXD pin RXsup 2100 1 05 ms 131 3 ms Matching data transmission interval CMtr1 28500 14 2 ms 1 78 ms Time from the echo back of matching data t...

Page 385: ...Control Pin I O Input Output Circuitry Remarks XIN XOUT Input Output Resonator connecting pins high frequency Rf 1 2 MΩ typ RO 0 5 kΩ typ XTIN XTOUT Input Output Resonator connecting pins Low frequency Rf 6 MΩ typ RO 220 kΩ typ RESET Input Hysteresis input Pull up resistor RIN 220 kΩ typ R 100 Ω typ TEST Input R 100 Ω typ fc Rf RO Osc enable XIN XOUT VDD VDD fs Rf RO Osc enable XTIN XTOUT VDD XTEN...

Page 386: ...00 Ω typ P5 I O Sink open drain output High current output Hysteresis input R 100 Ω typ P0 P4 I O Sink open drain output or C MOS output Hysteresis input R 100 Ω typ Initial High Z Disable Data output Pin input VDD R R Initial High Z Data output Output latch input Pin input VDD R Initial High Z Data output Output latch input Pin input R Initial High Z Data output Output latch input Pin input P ch ...

Page 387: ... P62 P61 P60 P7 I O Tri state I O R 100 Ω typ Port I O Input Output Circuitry Remarks Data output Disable VDD R Initial High Z Output latch input Key on Wakeup Analog input Pin input Data output Disable VDD R Initial High Z Output latch input Analog input Pin input ...

Page 388: ...Page 266 21 Input Output Circuit 21 2 Input Output Ports T5CL8 ...

Page 389: ...en designing products which include this device ensure that no absolute maximum rating value will ever be exceeded VSS 0 V Parameter Symbol Pins Ratings Unit Supply voltage VDD 0 3 to 6 0 V Input voltage VIN 0 3 to VDD 0 3 V Output voltage VOUT1 0 3 to VDD 0 3 V Output current Per 1 pin IOUT1 P0 P1 P4 P6 P7 ports 1 8 mA IOUT2 P0 P1 P2 P4 P6 P7 ports 3 2 IOUT3 P3 P5 ports 30 Output current Total Σ ...

Page 390: ...ngs Min Max Unit Supply voltage VDD NORMAL1 2 modes 4 5 5 5 V Input high level VIH1 Except hysteresis input VDD 4 5 V VDD 0 70 VDD VIH2 Hysteresis input VDD 0 75 Input low level VIL1 Except hysteresis input VDD 4 5 V 0 VDD 0 30 VIL2 Hysteresis input VDD 0 25 Clock frequency fc XIN XOUT 1 0 16 0 MHz VSS 0 V Topr 40 to 85 C Parameter Symbol Pins Ratings Min Max Unit Supply voltage VDD fc 16 MHz NORM...

Page 391: ...in Max Unit Supply voltage VDD NORMAL1 2 modes 4 5 5 5 V Input high voltage VIH1 Except hysteresis input VDD 4 5 V VDD 0 70 VDD VIH2 Hysteresis input VDD 0 75 Input low voltage VIL1 Except hysteresis input VDD 4 5 V 0 VDD 0 30 VIL2 Hysteresis input VDD 0 25 Clock frequency fc XIN XOUT 2 0 16 0 MHz ...

Page 392: ...VSS 0 V Topr 40 to 85 C Parameter Symbol Pins Condition Min Typ Max Unit Hysteresis voltage VHS Hysteresis input VDD 5 5 V VIN VTEST 5 5 V 0 V 0 9 V Input current IIN1 TEST 2 µA IIN2 Sink open drain tri state port IIN3 RESET STOP Input resistance RIN2 RESET pull up VDD 5 5 V VIN 0 V 100 220 450 kΩ Output leakage current ILO1 Sink open drain port VDD 5 5 V VOUT 5 5 V 2 µA ILO2 Tri state port VDD 5 ...

Page 393: ...n the flash memory the temperature must be kept within Topr 10 to 40 degree celsius If this temperature range is not observed operation cannot be guaranteed Figure 22 1 Intermittent Operation of Flash Memory Figure 22 2 Current When an Erase or Program is Being Performed on the Flash Memory n Program coutner PC n 1 n 2 n 3 1 machine cycle 4 fc or 4 fs MCU current I mA DDP P Typ current Momentary f...

Page 394: ... to 85 C Paramete Symbol Condition Min Typ Max Unit Analog reference voltage VAREF AVDD 1 0 AVDD V Power supply voltage of analog control circuit AVDD VDD Analog reference voltage range Note 4 VAREF 3 5 Analog input voltage VAIN VSS VAREF Power supply current of analog refer ence voltage IREF VDD AVDD VAREF 5 5 V VSS 0 0 V 0 6 1 0 mA Non linearity error VDD AVDD 5 0 V VSS 0 0 V VAREF 5 0 V 2 LSB Z...

Page 395: ...or external clock operation XTIN input fs 32 768 kHz 15 26 µs Low level clock pulse width tWSL VSS 0 V 2 7 V VDD 4 5 V Topr 40 to 85 C Paramete Symbol Condition Min Typ Max Unit Machine cycle time tcy NORMAL1 2 modes 0 5 4 µs IDLE0 1 2 modes SLOW1 2 modes 117 6 133 3 SLEEP0 1 2 modes High level clock pulse width tWCH For external clock operation XIN input fc 8 MHz 62 5 ns Low level clock pulse wid...

Page 396: ...ndling Precaution The solderability test conditions for lead free products indicated by the suffix G in product name are shown below 1 When using the Sn 37Pb solder bath Solder bath temperature 230 C Dipping time 5 seconds Number of times once R type flux used 2 When using the Sn 3 0Ag 0 5Cu solder bath Solder bath temperature 245 C Dipping time 5 seconds Number of times once R type flux used Note...

Page 397: ...Page 275 T5CL8 23 Package Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm ...

Page 398: ...Page 276 23 Package Dimensions T5CL8 ...

Page 399: ...y with version updates The recent advances in CMOS LSI production technology have been phenomenal and microcomputer systems for LSI design are constantly being improved The products described in this document may also be revised in the future Be sure to check the latest specifications before using Toshiba is developing highly integrated high performance microcomputers using advanced MOS production...

Page 400: ......

Page 401: ...data stores in 1MbitSRAM supplying the Voltage only to 1MbitSRAM Operation Temperature 20 70 C Package LQFP 80 Pin pitch 0 5 mm Micro controller interface 4bit parallel interface 6 lines CMOS silicon Monolithic LSI Head amplifier section CD DA R RW up to x2 speed Built in reference voltage VRO generation circuit Built in APC auto laser power control circuit Built in RF signal generation circuit En...

Page 402: ... coefficient RAM supporting various pickup types Built in focus and tracking servo control circuits Supports all search control modes thus realizing high speed stable searches Uses speed controlled lens kick and feed kick Built in AFC and APC circuits for disc motor CLV servo control Built in anti defect and anti shock circuits Support Stepper Motor Audio DSP section Incorporating firmware for pro...

Page 403: ...TC94B14MFG 2010 01 12 3 Pin Layout and Block Diagram Top View Pin Layout Top View TC94B14MFG Top View TEST1 ...

Page 404: ... F RF signal AGC amplifier input pin I 9 RFo O 3AI F RF signal generation amplifier output pin O 10 RVSS3 Grounding pin for 3 3 RF amplifier core and PLL circuit 11 FNI2 I 3AI F Main beam signal input pin To be connected to PIN diode C I 12 FNI1 I 3AI F Main beam signal input pin To be connected to PIN diode A I 13 FPI2 I 3AI F Main beam signal input pin To be connected to PIN diode D I 14 FPI1 I ...

Page 405: ...n output R 3 3 kΩ 31 DMo O 3AI F Disc servo equalizer output pin O Bulit in output R 3 3 kΩ 32 VDD1 3 I O 3I F Power supply pin for 1 5V Decoder DSP CD circuit 33 Pio8 TxD Dout I O 3I F Port 8 General Input Output Port HS UART Out Dout SPDIF I CMOS Port Schmitt input 34 Pio9 RxD Aout I O 3I F Port 9 General Input Output Port HS UART In Aout I CMOS Port Schmitt input 35 Pio10 RTS BCKo I O 3I F Port...

Page 406: ...r Supply pin for 3 3V clock oscillator circuit 51 VDD1 2 Power Supply pin for 1 5V Digital circuit 52 VSS Grounding pin for 1 5V digital circuit 53 Pio0 I O 3I F Port 0 General Input Output Port I CMOS Port Schmitt input 54 Pio1 I O 3I F Port 1 General Input Output Port I CMOS Port Schmitt input 55 Pio2 I O 3I F Port 2 General Input Output Port I CMOS Port Schmitt input 56 Pio3 I O 3I F Port 3 Gen...

Page 407: ...RAM circuit 75 PDo O 3AI F EFM and PLCK Phase difference signal output pin O 4 state output RVDD3 RVSS3 PVREF Hiz 76 TMAX O 3AI F TMAX detection result output pin O 3 state output RVDD3 RVSS3 Hiz 77 LPFN I 3AI F PLL circuit LPF amplifier inversion input pin I 78 LPFo O 3AI F PLL circuit LPF amplifier Output pin O 79 PVREF PLL circuit 1 65 V reference voltage pin Connected to VRO Connect to GND by ...

Page 408: ...crystal oscillation cycles before driving RST high To prevent the undefined pin states from affecting the servo circuitry or any other mechanical blocks in the system appropriate measures should be taken such as using a driver IC supporting a standby feature to place the system in standby mode before RST is driven high Note 3 Attach bypass capacitors of 0 1uF and 10uF between VDD pins and VSS pins...

Page 409: ...o8 DoUT 34 AoUT Pio9 AoUT 35 BCKo Pio10 BCKo 36 LRCKo Pio11 LRCKo 37 CDMON0 Pio12 AoUT AiN2 ZDET 38 CDMON1 Pio13 BCKo BCKi2 ZDET 39 CDMON2 Pio14 LRCKo LRCKi2 ZDET 40 CDMON3 ZDET See 2 Priority on CDMON Set up by PINMN command 2 CD CD Pin No Symbol CDMON CMD PINMN FGIN CMD BRKFG CD G CMD CLCKIEN CD TEXT CMD TEXTO Audio DSP Note 37 CDMON0 CDMON0 FGIN CLCKi 38 CDMON1 CDMON1 DATA TXSRCKi 39 CDMON2 CDM...

Page 410: ... be supplied at the same time within 100ms Characteristics Symbol Min Typ Max VDD3 rise time 1 tvd1 0 ms 100ms VDD1 fall time 2 tvd2 0 ms 100ms Power on reset period 1 Trst1 5 ms PLL setup period 1 tlock1 5 ms Power on reset period 2 Trst2 1 μs PLL setup period 2 Tlock2 5 ms Program boot waite period twait 0 ms Figure 2 1 Power on and initialization sequences ...

Page 411: ... so the SRAM standby mode is useful to implement a resume function to be used after the standby mode is exited Figure 3 1 shows the sequence of the SRAM standby mode Characteristics Symbol Min Typ Max VDD fall time 1 tvd1 0 ms 100ms VDD fall time 2 tvd2 1 μs VDD rise time 1 tvd3 0 ms 100ms HW reset period 1 trst 1 5 ms PLL setup period 1 tlock1 5 ms HW reset period 2 trst 2 1 μs PLL setup period 2...

Page 412: ...therwise specified Reference Ground Ta 25 C Characteristics Symbol Rating Unit Characteristics VDD3 0 3 3 8 Supply voltage VDD1 0 3 2 0 V VIN3 0 3 VDD3 0 3 Input voltage VIN1 0 3 3 9 V Power Dissipation PD 2674 mW Operating temperature C Storage temperature Tstg 55 150 C ...

Page 413: ...8 196 mV Operation reference voltage 1 VMDI1 VLDO VDD 1 3 V normal polarity LDO APCG H 150 178 206 mV LD off voltage 1 VLDOP1 VDD reference CMD LD OFF PNP 0 2 V Input bias current IAPC VMDI1 2 178 mV 1 1 μA RF section FPi1 FPi2 FNi1 FNi2 RFo GVA11RF RFOGAINi 0000 4 Voltage gain variable range 1 CD DA mode GVA12RF f 100 kHz CMD GVSW 1 RFOGAINi 1111 14 GVA21RF RFOGAINi 0000 8 Voltage gain variable r...

Page 414: ...D D7001E RFGC 00h f 100 700 kHz 100kHz step 100 ns Peak gain difference 11 1 speed mode Note 4 fV1EQ f 100 kHz reference RFGC B0h CMD D7C01E Boost Max 5 Peak gain difference 21 2 speed mode Note 4 fV2EQ f 100 kHz reference RFGC 00h CMD D7C11E Boost Max 5 dB Output slew rate SRAGC CRFEQO 20 pF 10 20 V us Output upper limit voltage VOHAGC GND reference 2 9 3 1 Output lower limit voltage VOLAGC GND r...

Page 415: ...ΔGVA2 FE 1 0 1 dB Frequency characteristic 1 CD DA mode fC1FE 3dB point CMD FEBW 0 CMD GVSW 1 29 Frequency characteristic 2 CD RW mode fC2FE 3dB point CMD FEBW 0 CMD GVSW 0 29 kHz Output offset voltage 1 CD DA mode Note 5 VOF1FE VRO reference FPI1 FPI2 FNI1 FNI2 open FEBC 00h CMD GVSW 1 50 50 Output offset voltage 2 CD RW mode Note 5 VOF2FE VRO reference FPI1 FPI2 FNI1 FNI2 open FEBC 00h CMD GVSW ...

Page 416: ...balance 1 CD DA mode GB1TE ΔGVA1 TE 1 0 1 Gain balance 2 CD RW mode GB2TE ΔGVA2 TE 1 0 1 dB Frequency characteristic 1 CD DA mode fC1TE 3dB point CMD GVSW 1 33 Frequency characteristic 2 CD RW mode fC2TE 3dB point CMD GVSW 0 33 kHz Output offset voltage 1 CD DA mode Note 6 VOF1TE VRO reference TPI TNI open TEBC 00h CMD GVSW 1 50 50 Output offset voltage 2 CD RW mode Note 6 VOF2TE VRO reference TPI...

Page 417: ...rence RFRPI 1 2Vpp 700 kHz 0 3 1 0 V Output upper limit voltage VOHRP GND reference 2 9 3 1 V Permissible load resistance RLMRP 10 15 kΩ RFDC section FPi1 FPi2 FNi1 FNi2 RFDC Detection frequency 1 Note 7 f1DC 3dB point with reference to low frequency side on the assumption that RFDCI 1 2 Vpp for VOP1DC and output amplitude 0dB for a 700 kHz sine wave input 20 kHz Detection constant 1 T1DC RFDCI 1 ...

Page 418: ...Voltage gain 2 CD RW mode GV1SB f 1kHz TEBC 00h CMD GVSW 0 SBADGAINi 1111 34 0 dB Frequency characteristic fCSB 3dB point 44 kHz Operating reference voltage 1 CD DA mode VOP1SB 1 1 0 8 0 5 Operating reference voltage 2 CD RW mode VOP2SB VRO reference No input SBADINV 0 1 1 0 8 0 5 V Output upper limit voltage ROHSB GND reference 2 9 3 1 Output lower limit voltage ROLSB GND reference 0 3 0 5 V Perm...

Page 419: ...100 IDD1 32 38 Operating power supply current 2 speed IDDM XI 16 9344 MHz fopr 85 MHz Note 8 CDMP3 opration MP3 Stream fs 48kHz 320 kbps Ta 20 70 Includs current for CD servo 0 6 1 mA H level VIH3 VDD3 x 0 7 L level VIL3 CMOS input pins 3 V circuits excluding analog input pins VDD3 x 0 3 H level VIH1 VDDM1 x 0 8 Input Voltage L level VIL1 SRMSTB pin VDDM1 x 0 2 V H level IIH3 VIH3 VDD3 2 0 Input c...

Page 420: ... value of table is reference value when operating CDMP3 standard application of operation speed 85MHz MP3 stream condition fs 48kHz 320kbps Characteristics Symbol Test Circuit Test Condition Min Typ Max Unit RO1 Pins listed at 3 in the following table 10 Output resistance integrated at pin RO2 Pins listed at 4 and 5 in the following table 3 3 kΩ Standby current ISTBM VDD1 VDD3 OFF VDDM 1 6 V SRMST...

Page 421: ...H pulse width tCC 150 Data disable time tSZ1 0 CCE BUCK delay time tCB 150 BUCK to CEE delay time tBC 150 BUCK cycle time tBUCK 800 BUCK L pulse width tBLW 400 BUCHK H pulse width tBHW 400 Write data set up time tWS 150 Write data hold time tWH 150 Read data access time tRD 150 ns CCEN ＢＵＣＫ BUSi tCB tWS tWH tBLW tBHW tBC tCC BUSi tRD tSZ1 tBUCK ...

Page 422: ...fs 170 BCKo Clock L Term width tBCOL CL 8pF fs 44 1kHz BCKo 64fs 170 BCKo standup falling term 1 tBCORF1 BCKo 35pin CL 8pF 15 BCKo standup falling term 2 tBCORF2 BCKo 38pin CL 8pF 8 LRCKo standup falling term 1 tLRCORF1 LRCKo 36pin CL 8pF 15 LRCKo standup falling term 2 tLRCORF2 LRCKo 39pin CL 8pF 8 AOUT Output delay time tDO CL 8 pF fs 44 1 kHz BCKo 64 fs 10 10 LRCKo Output delay time tDBLR CL 8 ...

Page 423: ... 2 L l e v e l tpHL2 CLCK Input mode 220 ns 2 CLCK output mode only for tHW tLW and tpLH3 n speed 1 n Characteristics Symbol Test Circuit Test Condition Min Typ Max Unit H l e v e l tHW 950 Clock pulse width L l e v e l tLW 950 Transfer time 1 L l e v e l tpHL1 70 H l e v e l tpLH2 70 Transfer time 2 L l e v e l tpHL2 70 Transfer time 3 H l e v e l tpLH3 CLCK Output mode 960 ns SUBQ SUBP SFSY CLCK...

Page 424: ...2 tor2 8 Falling time 2 tof2 Pio6 7 12 15 CL 8pF 8 MCKo Clock time TBCO 58 MCKo Clock H time TBCOH 25 MCKo Clock H time TBCOL CL 8pF fs 44 1kHz MCKo 384fs Xi 25 ns Characteristics Symbol Test Circuit Test Condition Min Typ Max Unit H l e v e l tpLH1 500 Transfer time 1 L l e v e l tpHL1 SBSY 500 H l e v e l tpLH2 500 Transfer time 2 L l e v e l tpHL2 SBOK 500 ns SFSY SBSY SBOK tpLH2 tpHL2 tpLH1 tp...

Page 425: ...ocus and Tracking Sections Characteristics Test Circuit Test Condition Min Typ Max Unit Bit number 5 bit Sampling frequency 5 6 MHz Output signal range AVSS 0 V AVDD3 3 3 V AVSS3 AVDD3 V 5 4 3 PLL Section Filter Amp Characteristics Test Circuit Test Condition Min Typ Max Unit Input output signal range RVSS3 RVDD3 V Frequency characteristic 3dB point Gain 1 1 7 MHz 5 4 4 VCO PLL Characteristics Tes...

Page 426: ...put range AVSS3 AVDD3 V Hysteresis voltage VREF reference 50 mV 5 4 7 Data Slicer Circuit 1 Comparator Characteristics Test Circuit Test Condition Min Typ Max Unit Input amplitude VREF reference 0 6 1 2 2 0 Vpp 2 R 2R DAC DAC for digital slicer Characteristics Test Circuit Test Condition Min Typ Max Unit Output conversation range SLCOG 0 3 4 VREF 5 4 VREF V Output conversation range SLCOG 1 1 2 VR...

Page 427: ...z sine wave full scale input 780 820 860 mVrms Stop band Attenuation 60dB In band ripple below 0 025dB This characteristic is the characteristic at the time of 1x Playback mode Test circuit 1 The application circuit shown in the following example is used Characteristics Distortion Filter Setting A weight THD N CT OFF S N DR ON A weight IEC A or equivalent Application circuit example XVSS3 XVDD3 Xi...

Page 428: ...TC94B14MFG 2010 01 12 28 Package LQFP80 P 1212 0 50F Weight 0 6 g Typical ...

Page 429: ...rmed Solderability 1 Use of Sn 37Pb solder Bath solder bath temperature 230 C dipping time 5 seconds the number of times once use of R type flux 2 Use of Sn 3 0Ag 0 5Cu solder Bath solder bath temperature 245 C dipping time 5 seconds the number of times once use of R type flux ...

Page 430: ...acilities equipment used in the aerospace industry medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators devices related to electric power and equipment used in finance related fields Do not use Product for Unintended Use unless specifically permi...

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