Philips CEM2100/00, Service Manual

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9.3.2 Event counter mode
In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are com-
pared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the
counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is
cleared.
Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at
the falling edge after the match of TC2DR and up counter.
The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required
for both the “H” and “L” levels of the pulse width.
Figure 9-3 Event Counter Mode Timing Chart
9.3.3 Window mode
In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input
(Window pulse) is “H” level. The contents of TC2DR are compared with the contents of up counter. If a match
found, an INTTC2 interrupt is generated, and the up-counter is cleared.
The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock
by the TC2CR<TC2CK>.
Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL
mode, the timer should be halted by setting TC2CR<TC2S> to "0" before the SLOW/SLEEP mode is entered.
Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.
LDW (TC2DR), 640 ; Sets TC2DR
DI ; IMF= “0”
SET (EIRE). 6 ;Enables INTTC2 interrupt
EI ; IMF= “1”
LD (TC2CR), 00011100B ; TC2 source vclock / mode select
LD (TC2CR), 00111100B ; Starts TC2
Table 9-2 Timer/Counter 2 External Input Clock Pulse Width
Minimum Input Pulse Width [s]
NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode
“H” width
2
3
/fc 2
3
/fs
“L” width
2
3
/fc 2
3
/fs
n
INTTC2 interrupt
TC2 pin input
Counter
TC2DR
Match detect
Counter clear
Timer start
0 1 2 3 n 0 1 2 3