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12. Asynchronous Serial interface (UART1 )
12.6 STOP Bit Length
T
5CL8
12.6 STOP Bit Length
Select a transmit stop bit length (1 bit or 2 bits) by UART1CR1<STBT>.
12.7 Parity
Set parity / no parity by UART1CR1<PE> and set parity type (Odd- or Even-numbered) by
UART1CR1<EVEN>.
12.8 Transmit/Receive Operation
12.8.1 Data Transmit Operation
Set UART1CR1<TXE> to “1”. Read UART1SR to check UART1SR<TBEP> = “1”, then write data in
TD1BUF (Transmit data buffer). Writing data in TD1BUF zero-clears UART1SR<TBEP>, transfers the data
to the transmit shift register and the data are sequentially output from the TXD1 pin. The data output include a
one-bit start bit, stop bits whose number is specified in UART1CR1<STBT> and a parity bit if parity addition
is specified. Select the data transfer baud rate using UART1CR1<BRG>. When data transmit starts, transmit
buffer empty flag UART1SR<TBEP> is set to “1” and an INTTXD1 interrupt is generated.
While UART1CR1<TXE> = “0” and from when “1” is written to UART1CR1<TXE> to when send data are
written to TD1BUF, the TXD1 pin is fixed at high level.
When transmitting data, first read UART1SR, then write data in TD1BUF. Otherwise, UART1SR<TBEP> is
not zero-cleared and transmit does not start.
12.8.2 Data Receive Operation
Set UART1CR1<RXE> to “1”. When data are received via the RXD1 pin, the receive data are transferred to
RD1BUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RD1BUF (Receive data buffer). Then the receive buffer full flag UART1SR<RBFL> is set and an INTRXD1
interrupt is generated. Select the data transfer baud rate using UART1CR1<BRG>.
If an overrun error (OERR) occurs when data are received, the data are not transferred to RD1BUF (Receive
data buffer) but discarded; data in the RD1BUF are not affected.
Note:When a receive operation is disabled by setting UART1CR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
Summary of Contents for CEM2100/00
Page 2: ...2 ...
Page 3: ...BLOCK DIAGRAM ...
Page 4: ...WIRING DIAGRAM 4 ...
Page 5: ...CIRCUIT DIAGRAM MAIN BOARD 5 ...
Page 6: ...6 ...
Page 7: ......
Page 11: ...PCB LAYOUT MAIN BOARD TOP SIDE VIEW 11 ...
Page 12: ...PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW 12 ...
Page 13: ...PCB LAYOUT PANEL BOARD TOP SIDE VIEW ...
Page 14: ...14 PCB LAYOUT PANEL BOARD BOTTOM SIDE VIEW ...
Page 15: ...PCB LAYOUT REMOTE BOARD TOP SIDE VIEW 15 ...
Page 16: ...PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW 16 ...
Page 17: ...PCB LAYOUT TUNER BOARD TOP SIDE VIEW 17 ...
Page 18: ...PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 18 ...
Page 19: ...PCB LAYOUT SD BOARD TOP SIDE VIEW ...
Page 20: ...20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW ...
Page 21: ...PCB LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 ...
Page 22: ...22 SET EXPLODER VIEW DRAWING ...
Page 23: ...1 of 2 CEM2100 Trouble shooting Trouble shooting Trouble shooting Trouble shooting ...
Page 33: ...7 0 6SHFLILFDWLRQ 6 VWHP EORFN GLDJUDP ...
Page 110: ...7 0 6SHFLILFDWLRQ 5HYLVLRQ KLVWRU 2 2 s u 2 u 2 7 t 2 2 2 S S 5 2 v 2 2 ...
Page 111: ...8 Bit Microcontroller TLCS 870 C Series T5CL8 ...
Page 113: ...Revision History Date Revision 2008 7 31 1 First Release ...
Page 114: ......
Page 122: ...viii ...
Page 126: ...Page 4 1 3 Block Diagram T5CL8 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 130: ...Page 8 1 4 Pin Names and Functions T5CL8 ...
Page 155: ...Page 33 T5CL8 ...
Page 156: ...Page 34 2 Operational Description 2 3 Reset Circuit T5CL8 ...
Page 186: ...Page 64 5 I O Ports 5 8 Port P7 P77 to P70 T5CL8 ...
Page 194: ...Page 72 6 Watchdog Timer WDT 6 3 Address Trap T5CL8 ...
Page 214: ...Page 92 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 ...
Page 270: ...Page 148 12 Asynchronous Serial interface UART1 12 9 Status Flag T5CL8 ...
Page 280: ...Page 158 13 Asynchronous Serial interface UART2 13 9 Status Flag T5CL8 ...
Page 332: ...Page 210 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 ...
Page 342: ...Page 220 17 10 bit AD Converter ADC 17 6 Precautions about AD Converter T5CL8 ...
Page 354: ...Page 232 19 Flash Memory 19 4 Access to the Flash Memory Area T5CL8 ...
Page 388: ...Page 266 21 Input Output Circuit 21 2 Input Output Ports T5CL8 ...
Page 397: ...Page 275 T5CL8 23 Package Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm ...
Page 398: ...Page 276 23 Package Dimensions T5CL8 ...
Page 400: ......
Page 428: ...TC94B14MFG 2010 01 12 28 Package LQFP80 P 1212 0 50F Weight 0 6 g Typical ...