Philips CEM2100/00, Service Manual

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Page 197
T
5CL8
16.5 I
2
C Bus Control
The following registers are used to control the serial bus interface and monitor the operation status of the I
2
C bus.
Note 1: fc: High-frequency clock [Hz], *: Don't care
Note 2: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3: Do not set SCK as the frequency that is over 100 kHz.
Note 1: For writing transmitted data, start from the MSB (Bit7).
Note 2: The data which was written into SBIDBR can not be read, since a write data buffer and a read buffer are independent in
SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3: *: Don't care
Serial Bus Interface Control Register A
SBICRA
(0F90H)
7 6 5 4 3 2 1 0
BC ACK SCK (Initial value: 0000 *000)
BC Number of transferred bits
BC
ACK = 0 ACK = 1
Write
only
Number of
Clock
Bits
Number of
Clock
Bits
000: 8 8 9 8
001: 1 1 2 1
010: 2 2 3 2
011: 3 3 4 3
100: 4 4 5 4
101: 5 5 6 5
110: 6 6 7 6
111: 7 7 8 7
ACK
Acknowledgement mode
specification
ACK Master mode Slave mode
R/W
0:
Not generate a clock pulse for
an acknowledgement. Not count a clock pulse for
an acknowledgement.
1:
Generate a clock pulse for an
acknowledgement. Count a clock pulse for an
acknowledgement.
SCK
Serial clock (fscl) selection
(Output on SCL pin)
[fscl = 1/(2
n+1
/fc + 8/fc)]
SCK n At fc = 16 MHz At fc = 8 MHz At fc = 4 MHz
Write
only
000: 4 Reserved Reserved 100.0 kHz
001: 5 Reserved Reserved 55.6 kHz
010: 6 Reserved 58.8 kHz 29.4 kHz
011: 7 60.6 kHz 30.3 kHz 15.2 kHz
100: 8 30.8 kHz 15.4 kHz 7.7 kHz
101: 9 15.5 kHz 7.8 kHz 3.9 kHz
110: 10 7.8 kHz 3.9 kHz 1.9 kHz
111: Reserved
Serial Bus Interface Data Buffer Register
SBIDBR
(0F91H)
7 6 5 4 3 2 1 0
(Initial value: **** ****) R/W