Philips CEM2100/00, Service Manual

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Page 35
T
5CL8
3. Interrupt Control Circuit
The T
5CL8
has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities.
Four of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 3: If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is
being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed. For details,
refer to the corresponding notes in the chapter on the AD converter.
3.1 Interrupt latches (IL23 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
Interrupt Factors Enable Condition
Interrupt
Latch
Vector
Address
Priority
Internal/External (Reset) Non-maskable – FFFE 1
Internal INTSWI (Software interrupt) Non-maskable – FFFC 2
Internal
INTUNDEF (Executed the undefined instruction
interrupt)
Non-maskable – FFFC 2
Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2
Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2
External
INT0
IMF• EF4 = 1, INT0EN = 1 IL4 FFF6 5
Internal INTTC1 IMF• EF5 = 1 IL5 FFF4 6
External INT1 IMF• EF6 = 1 IL6 FFF2 7
Internal INTTBT IMF• EF7 = 1 IL7 FFF0 8
External INT2 IMF• EF8 = 1 IL8 FFEE 9
Internal INTTC4 IMF• EF9 = 1 IL9 FFEC 10
Internal INTTC3 IMF• EF10 = 1 IL10 FFEA 11
Internal INTSBI IMF• EF11 = 1 IL11 FFE8 12
External INT3 IMF• EF12 = 1 IL12 FFE6 13
Internal INTSIO1 IMF• EF13 = 1 IL13 FFE4 14
Internal INTSIO2 IMF• EF14 = 1 IL14 FFE2 15
Internal INTADC IMF• EF15 = 1 IL15 FFE0 16
Internal INTRXD1 IMF• EF16 = 1 IL16 FFBE 17
Internal INTTXD1 IMF• EF17 = 1 IL17 FFBC 18
Internal INTTC6 IMF• EF18 = 1 IL18 FFBA 19
Internal INTTC5 IMF• EF19 = 1 IL19 FFB8 20
Internal INTRXD2 IMF• EF20 = 1 IL20 FFB6 21
Internal INTTXD2 IMF• EF21 = 1 IL21 FFB4 22
Internal INTTC2 IMF• EF22 = 1 IL22 FFB2 23
External
INT5
IMF• EF23 = 1 IL23 FFB0 24