Philips CEM2100/00, Service Manual

Page: 131 / 430

Page 9
T
5CL8
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1 Memory Address Map
The
T5CL8
memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special func-
tion register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
T5CL8
memory
address map.
Figure 2-1 Memory Address Map
2.1.2 Program Memory (Flash)
The
T5CL8
has a 61440 bytes (Address 1000H to FFFFH) of program memory (Flash ).
2.1.3 Data Memory (RAM)
The
T5CL8
has 2048 bytes (Address 0040H to 083FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.
SFR
0000
H
64 bytes
SFR:
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
003F
H
RAM
0040
H
2048
bytes
083F
H
DBR
0F80
H
128
bytes
DBR: Data buffer register includes:
Peripheral control registers
Peripheral status registers
0FFF
H
1000
H
Flash:
Program memory
Flash
61440
bytes
FFB0
H
Vector table for interrupts
(16 bytes)
FFBF
H
FFC0
H
Vector table for vector call instructions
(32 bytes)
FFDF
H
FFE0
H
Vector table for interrupts
(32 bytes)
FFFF
H