Philips CEM2100/00, Service Manual

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Page 78
8. 16-Bit TimerCounter 1 (TC1)
8.2 TimerCounter Control
T
5CL8
8.2 TimerCounter Control
The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers
(TC1DRA and TC1DRB).
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the
first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower
byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only
the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register.
Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR during TC1S=00. Set the timer F/
F1 control until the first timer start after setting the PPG mode.
Timer Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TC1DRA
(0011H, 0010H)
TC1DRAH (0011H) TC1DRAL (0010H)
(Initial value: 1111 1111 1111 1111) Read/Write
TC1DRB
(0013H, 0012H)
TC1DRBH (0013H) TC1DRBL (0012H)
(Initial value: 1111 1111 1111 1111) Read/Write (Write enabled only in the PPG output mode)
TimerCounter 1 Control Register
TC1CR
(0026H)
7 6 5 4 3 2 1 0
TFF1
ACAP1
MCAP1
METT1
MPPG1
TC1S TC1CK TC1M
Read/Write
(Initial value: 0000 0000)
TFF1 Timer F/F1 control 0: Clear 1: Set R/W
ACAP1 Auto capture control 0:Auto-capture disable 1:Auto-capture enable
R/W
MCAP1
Pulse width measure-
ment mode control
0:Double edge capture 1:Single edge capture
METT1
External trigger timer
mode control
0:Trigger start 1:Trigger start and stop
MPPG1 PPG output control 0:Continuous pulse generation 1:One-shot
TC1S TC1 start control
Timer
Extrig-
ger
Event
Win-
dow
Pulse PPG
R/W
00: Stop and counter clear O O O O O O
01: Command start O – – – – O
10: Rising edge start
(Ex-trigger/Pulse/PPG)
Rising edge count (Event)
Positive logic count (Window)
– O O O O O
11: Falling edge start
(Ex-trigger/Pulse/PPG)
Falling edge count (Event)
Negative logic count (Window)
– O O O O O
TC1CK
TC1 source clock select
[Hz]
NORMAL1/2, IDLE1/2 mode
Divider
SLOW,
SLEEP
mode
R/W
DV7CK = 0 DV7CK = 1
00
fc/2
11
fs/2
3
DV9
fs/2
3
01
fc/2
7
fc/2
7
DV5 –
10
fc/2
3
fc/2
3
DV1 –
11 External clock (TC1 pin input)
TC1M
TC1 operating mode
select
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
R/W