Page 203
T
5CL8
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
• At the end of acknowledge signal when the received slave address matches to the value set by the
I2CAR
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
CALL”
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISRB) is cleared to “0”. During the
time that the PIN is “0”, the SCL pin is pulled-down to low level.
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes t
LOW
.
Although the PIN (Bit4 in SBICRB) can be set to “1” by the softrware, the PIN can not be cleared to “0” by
the softrware.
Note:When the arbitration lost occurs, if the slave address sent from the other master devices is not match, the
INTSBI interrupt request is generated. But the PIN is not cleared.
16.5.9 Setting of I
2
C bus mode
The SBIM (Bit3 and 2 in SBICRB) is used to set I
2
C bus mode.
Set the SBIM to “10” in order to set I
2
C bus mode. Before setting of I
2
C bus mode, confirm serial bus inter-
face pins in a high level, and then, write “10” to SBIM. And switch a port mode after confirming that a bus is
free.
16.5.10Arbitration lost detection monitor
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple-
mented in order to guarantee the contents of transferred data.
Data on the SDA line is used for bus arbitration of the I
2
C bus.
The following shows an example of a bus arbitration procedure when two master devices exist simulta-
neously on a bus. Master 1 and Master 2 output the same data until point “a”. After that, when Master 1 outputs
“1” and Master 2 outputs “0”, since the SDA line of a bus is wired AND, the SDA line is pulled-down to the
low level by Master 2. When the SCL line of a bus is pulled-up at point “b”, the slave device reads data on the
SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is
called “arbitration lost”. A master device which loses arbitration releases the SDA pin and the SCL pin in order
not to effect data transmitted from other masters with arbitration. When more than one master sends the same
data at the first word, arbitration occurs continuously after the second word.
Figure 16-7 Arbitration Lost
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
the SCL line. If the levels are unmatched, arbitration is lost and the AL (Bit3 in SBISRB) is set to “1”.
a
b
SCL (Bus)
SDA pin (Master 1)
SDA pin (Master 2)
SDA (Bus)
SDA pin becomes "1" after losing arbitration.
Summary of Contents for CEM2100/00
Page 2: ...2 ...
Page 3: ...BLOCK DIAGRAM ...
Page 4: ...WIRING DIAGRAM 4 ...
Page 5: ...CIRCUIT DIAGRAM MAIN BOARD 5 ...
Page 6: ...6 ...
Page 7: ......
Page 11: ...PCB LAYOUT MAIN BOARD TOP SIDE VIEW 11 ...
Page 12: ...PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW 12 ...
Page 13: ...PCB LAYOUT PANEL BOARD TOP SIDE VIEW ...
Page 14: ...14 PCB LAYOUT PANEL BOARD BOTTOM SIDE VIEW ...
Page 15: ...PCB LAYOUT REMOTE BOARD TOP SIDE VIEW 15 ...
Page 16: ...PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW 16 ...
Page 17: ...PCB LAYOUT TUNER BOARD TOP SIDE VIEW 17 ...
Page 18: ...PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 18 ...
Page 19: ...PCB LAYOUT SD BOARD TOP SIDE VIEW ...
Page 20: ...20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW ...
Page 21: ...PCB LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 ...
Page 22: ...22 SET EXPLODER VIEW DRAWING ...
Page 23: ...1 of 2 CEM2100 Trouble shooting Trouble shooting Trouble shooting Trouble shooting ...
Page 33: ...7 0 6SHFLILFDWLRQ 6 VWHP EORFN GLDJUDP ...
Page 110: ...7 0 6SHFLILFDWLRQ 5HYLVLRQ KLVWRU 2 2 s u 2 u 2 7 t 2 2 2 S S 5 2 v 2 2 ...
Page 111: ...8 Bit Microcontroller TLCS 870 C Series T5CL8 ...
Page 113: ...Revision History Date Revision 2008 7 31 1 First Release ...
Page 114: ......
Page 122: ...viii ...
Page 126: ...Page 4 1 3 Block Diagram T5CL8 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 130: ...Page 8 1 4 Pin Names and Functions T5CL8 ...
Page 155: ...Page 33 T5CL8 ...
Page 156: ...Page 34 2 Operational Description 2 3 Reset Circuit T5CL8 ...
Page 186: ...Page 64 5 I O Ports 5 8 Port P7 P77 to P70 T5CL8 ...
Page 194: ...Page 72 6 Watchdog Timer WDT 6 3 Address Trap T5CL8 ...
Page 214: ...Page 92 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 ...
Page 270: ...Page 148 12 Asynchronous Serial interface UART1 12 9 Status Flag T5CL8 ...
Page 280: ...Page 158 13 Asynchronous Serial interface UART2 13 9 Status Flag T5CL8 ...
Page 332: ...Page 210 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 ...
Page 342: ...Page 220 17 10 bit AD Converter ADC 17 6 Precautions about AD Converter T5CL8 ...
Page 354: ...Page 232 19 Flash Memory 19 4 Access to the Flash Memory Area T5CL8 ...
Page 388: ...Page 266 21 Input Output Circuit 21 2 Input Output Ports T5CL8 ...
Page 397: ...Page 275 T5CL8 23 Package Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm ...
Page 398: ...Page 276 23 Package Dimensions T5CL8 ...
Page 400: ......
Page 428: ...TC94B14MFG 2010 01 12 28 Package LQFP80 P 1212 0 50F Weight 0 6 g Typical ...