Page 207
T
5CL8
To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1-
word before the last data to be received. A serial bus interface circuit does not generate a clock pulse
for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when
the BC is set to “001” and read the data, PIN is set to “1” and generates a clock pulse for a 1-bit data
transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-level.
The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the trans-
mitter that data transfer is complete.
After 1-bit data is received and an interrupt request has occurred, generate the stop condition to ter-
minate data transfer.
Figure 16-12 Termination of Data Transfer in Master Receiver Mode
16.6.3.2 When the MST is “0” (Slave mode)
In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode
after losing arbitration.
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
• At the end of acknowledge signal when the received slave address matches to the value set by the
I2CAR
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
CALL”
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an
INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior
of INTSBI interrupt request and PIN after losing arbitration are shown in Table 16-3.
When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICRB) is reset, and the SCL pin is set
to low level. Either reading or writing from or to the SBIDBR or setting the PIN to “1” releases the SCL
pin after taking t
LOW
.
Table 16-3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration
When the Arbitration Lost Occurs during Trans-
mission of Slave Address as a Master
When the Arbitration Lost Occurs during Trans-
mission of Data as a Master Transmit Mode
INTSBI
interrupt
request
INTSBI interrupt request is generated at the termination of word data.
PIN
When the slave address matches the value set
by I2CAR, the PIN is cleared to "0" by generating
of INTSBI interrupt request. When the slave
address doesn't match the value set by I2CAR,
the PIN keeps "1".
PIN keeps "1" (PIN is not cleared to "0").
D7
D6
2
3
4
5
6
7
8
1
D5
D4
D2
D3
D1
D0
1
Acknowledge signal
sent to a transmitter
SCL pin
SDA pin
PIN
INTSBI
interrupt request
Clear ACK to "0"
before reading SBIDBR
Set BC to "001"
before reading SBIDBR
Summary of Contents for CEM2100/00
Page 2: ...2 ...
Page 3: ...BLOCK DIAGRAM ...
Page 4: ...WIRING DIAGRAM 4 ...
Page 5: ...CIRCUIT DIAGRAM MAIN BOARD 5 ...
Page 6: ...6 ...
Page 7: ......
Page 11: ...PCB LAYOUT MAIN BOARD TOP SIDE VIEW 11 ...
Page 12: ...PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW 12 ...
Page 13: ...PCB LAYOUT PANEL BOARD TOP SIDE VIEW ...
Page 14: ...14 PCB LAYOUT PANEL BOARD BOTTOM SIDE VIEW ...
Page 15: ...PCB LAYOUT REMOTE BOARD TOP SIDE VIEW 15 ...
Page 16: ...PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW 16 ...
Page 17: ...PCB LAYOUT TUNER BOARD TOP SIDE VIEW 17 ...
Page 18: ...PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 18 ...
Page 19: ...PCB LAYOUT SD BOARD TOP SIDE VIEW ...
Page 20: ...20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW ...
Page 21: ...PCB LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 ...
Page 22: ...22 SET EXPLODER VIEW DRAWING ...
Page 23: ...1 of 2 CEM2100 Trouble shooting Trouble shooting Trouble shooting Trouble shooting ...
Page 33: ...7 0 6SHFLILFDWLRQ 6 VWHP EORFN GLDJUDP ...
Page 110: ...7 0 6SHFLILFDWLRQ 5HYLVLRQ KLVWRU 2 2 s u 2 u 2 7 t 2 2 2 S S 5 2 v 2 2 ...
Page 111: ...8 Bit Microcontroller TLCS 870 C Series T5CL8 ...
Page 113: ...Revision History Date Revision 2008 7 31 1 First Release ...
Page 114: ......
Page 122: ...viii ...
Page 126: ...Page 4 1 3 Block Diagram T5CL8 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 130: ...Page 8 1 4 Pin Names and Functions T5CL8 ...
Page 155: ...Page 33 T5CL8 ...
Page 156: ...Page 34 2 Operational Description 2 3 Reset Circuit T5CL8 ...
Page 186: ...Page 64 5 I O Ports 5 8 Port P7 P77 to P70 T5CL8 ...
Page 194: ...Page 72 6 Watchdog Timer WDT 6 3 Address Trap T5CL8 ...
Page 214: ...Page 92 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 ...
Page 270: ...Page 148 12 Asynchronous Serial interface UART1 12 9 Status Flag T5CL8 ...
Page 280: ...Page 158 13 Asynchronous Serial interface UART2 13 9 Status Flag T5CL8 ...
Page 332: ...Page 210 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 ...
Page 342: ...Page 220 17 10 bit AD Converter ADC 17 6 Precautions about AD Converter T5CL8 ...
Page 354: ...Page 232 19 Flash Memory 19 4 Access to the Flash Memory Area T5CL8 ...
Page 388: ...Page 266 21 Input Output Circuit 21 2 Input Output Ports T5CL8 ...
Page 397: ...Page 275 T5CL8 23 Package Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm ...
Page 398: ...Page 276 23 Package Dimensions T5CL8 ...
Page 400: ......
Page 428: ...TC94B14MFG 2010 01 12 28 Package LQFP80 P 1212 0 50F Weight 0 6 g Typical ...