Page 43
T
5CL8
3.7 External Interrupts
The T
5CL8
has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The
INT0
/P00 pin can be configured as either an external inter-
rupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and
INT0
/P00 pin function selection are performed by the external interrupt
control register (EINTCR).
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig-
nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the
INT0
pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an inter-
rupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Source
Pin
Enable Conditions
Release Edge
Digital Noise Reject
INT0
INT0
IMF
EF4
INT0EN=1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT1
INT1
IMF
EF6 = 1
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are elimi-
nated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
INT2
INT2
IMF
EF8 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT3
INT3
IMF
EF12 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT5
INT5
IMF
EF23 = 1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Summary of Contents for CEM2100/00
Page 2: ...2 ...
Page 3: ...BLOCK DIAGRAM ...
Page 4: ...WIRING DIAGRAM 4 ...
Page 5: ...CIRCUIT DIAGRAM MAIN BOARD 5 ...
Page 6: ...6 ...
Page 7: ......
Page 11: ...PCB LAYOUT MAIN BOARD TOP SIDE VIEW 11 ...
Page 12: ...PCB LAYOUT MAIN BOARD BOTTOM SIDE VIEW 12 ...
Page 13: ...PCB LAYOUT PANEL BOARD TOP SIDE VIEW ...
Page 14: ...14 PCB LAYOUT PANEL BOARD BOTTOM SIDE VIEW ...
Page 15: ...PCB LAYOUT REMOTE BOARD TOP SIDE VIEW 15 ...
Page 16: ...PCB LAYOUT REMOTE BOARD BOTTOM SIDE VIEW 16 ...
Page 17: ...PCB LAYOUT TUNER BOARD TOP SIDE VIEW 17 ...
Page 18: ...PCB LAYOUT TUNER BOARD BOTTOM SIDE VIEW 18 ...
Page 19: ...PCB LAYOUT SD BOARD TOP SIDE VIEW ...
Page 20: ...20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW ...
Page 21: ...PCB LAYOUT ISO BOARD BOTTOM SIDE VIEW 21 ...
Page 22: ...22 SET EXPLODER VIEW DRAWING ...
Page 23: ...1 of 2 CEM2100 Trouble shooting Trouble shooting Trouble shooting Trouble shooting ...
Page 33: ...7 0 6SHFLILFDWLRQ 6 VWHP EORFN GLDJUDP ...
Page 110: ...7 0 6SHFLILFDWLRQ 5HYLVLRQ KLVWRU 2 2 s u 2 u 2 7 t 2 2 2 S S 5 2 v 2 2 ...
Page 111: ...8 Bit Microcontroller TLCS 870 C Series T5CL8 ...
Page 113: ...Revision History Date Revision 2008 7 31 1 First Release ...
Page 114: ......
Page 122: ...viii ...
Page 126: ...Page 4 1 3 Block Diagram T5CL8 1 3 Block Diagram Figure 1 2 Block Diagram ...
Page 130: ...Page 8 1 4 Pin Names and Functions T5CL8 ...
Page 155: ...Page 33 T5CL8 ...
Page 156: ...Page 34 2 Operational Description 2 3 Reset Circuit T5CL8 ...
Page 186: ...Page 64 5 I O Ports 5 8 Port P7 P77 to P70 T5CL8 ...
Page 194: ...Page 72 6 Watchdog Timer WDT 6 3 Address Trap T5CL8 ...
Page 214: ...Page 92 8 16 Bit TimerCounter 1 TC1 8 3 Function T5CL8 ...
Page 270: ...Page 148 12 Asynchronous Serial interface UART1 12 9 Status Flag T5CL8 ...
Page 280: ...Page 158 13 Asynchronous Serial interface UART2 13 9 Status Flag T5CL8 ...
Page 332: ...Page 210 16 Serial Bus Interface I2C Bus Ver D SBI 16 6 Data Transfer of I2C Bus T5CL8 ...
Page 342: ...Page 220 17 10 bit AD Converter ADC 17 6 Precautions about AD Converter T5CL8 ...
Page 354: ...Page 232 19 Flash Memory 19 4 Access to the Flash Memory Area T5CL8 ...
Page 388: ...Page 266 21 Input Output Circuit 21 2 Input Output Ports T5CL8 ...
Page 397: ...Page 275 T5CL8 23 Package Dimensions LQFP64 P 1010 0 50D Rev 01 Unit mm ...
Page 398: ...Page 276 23 Package Dimensions T5CL8 ...
Page 400: ......
Page 428: ...TC94B14MFG 2010 01 12 28 Package LQFP80 P 1212 0 50F Weight 0 6 g Typical ...