GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 99 of 123
9
Appendix B: Return Path Optimization Using Anritsu
J1890A PCIe5 Re-Driver Set
It is important to optimize the Return Path (DUT Tx to BERT Error Detector) when testing for
Receiver Link Equalization with PCIe Gen5 (32 GT/s), as described below.
9.1
Requirements for Using an External Driver (J1890A)
When testing the System Board, connect the J1890A PCIe5 Re-Driver Set between the DUT Tx and
BERT Error Detector. Refer to Section 9.3 for information on how to set up the J1890A PCIe5 Re-
Driver Set.
Note
: While it is not necessary to use a Re-Driver for the Add-In Card Rx Link EQ Test, the same
method of optimizing the Return Path should apply when testing the System Board or Add-In Card.
9.2
Return Path Optimization Procedure
Follow the steps below to optimize the Return Path.
1.
Connect the equipment as shown in the System TxRx Link EQ Test setups in Section 5.5.1 &
5.6.1 or Section 8.2.2 & 8.3.2 respectively.
2.
Start the MX1830
00A, set the ‘Specification’ to ‘Gen5’, and then turn off all stresses as follows:
•
SJ
•
RJ
•
DMI
•
CMI
3.
Select the
‘
LEQ Test Setting
’
checkbox in the MX183000A Main Window and set the following:
i)
Set
‘
PPG Starting Preset
’
to
‘
P5
’
