GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 11 of 123
1
Introduction
This user manual provides information using the GRL-PCIE5-CEM-RXA test automation solution to
set up and test an electrical receiver (Rx) device to meet PCI Express Card Electromechanical
(CEM) 5.0 compliance for 32 GT/s as per PCI Express (PCI-SIG) Standards.
The main body of this documentation first describes how to configure the GRL-PCIE5-CEM-RXA
test software to calibrate the stressed eye at the receiver of the device under test (DUT) in the PCIe
Gen 5.0 system. This includes calibration to be performed at both the physical Test Point 3 (TP3)
and the Long Channel at TP2. The GRL software will automate calibration without channel effect
at TP3 before measuring the eye opening due to trace length. It also enables running the SigTest
and Seasim post processing analysis application to ensure signal quality compliance. The final
calibrated eye diagram uses both the SigTest and Seasim software to achieve the final stressed
eye calibration.
After completing calibration, the GRL-PCIE5-CEM-RXA software will automate compliance testing
for the receiver using Bit Error Ratio (BER) as a metric. The receiver path is tested with worst case
eye to ensure a BER of less than 1E-12 can be achieved. The software also provides an optional SJ
margin search test for the DUT.
The GRL-PCIE5-CEM-RXA software performs test automation according to PCI-SIG-approved
Methods of Implementation (MOI
’
s) with high performance real-time oscilloscopes and Anritsu
BERT using existing PCI-SIG Compliance Base Boards (CBB
’s) and Compliance
Load Boards
(CLB
’
s). The GRL software is run from the computer or oscilloscope to provide automation control
to test the DUT for PCIe CEM 5.0 Rx electrical compliance. When combined with a satisfactory level
of interoperability testing, these tests provide a reasonable level of confidence that the DUT
’
s will
function properly in most PCIe environments.
Note: For manual test methodology, refer to Appendix of this documentation or PCI-SIG for approved
Method of Implementation (MOI
’
s) as technical reference.
