GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 39 of 123
F
IGURE
25.
M
AIN
S
TATE
D
IAGRAM FOR
L
INK
T
RAINING AND
S
TATUS
S
TATE
M
ACHINE
(
FROM
PHY
T
EST
S
PECIFICATION
)
Below is a loopback training sequence example from PHY Test Specification:
F
IGURE
26.
P
OLLING
S
UBSTATE
M
ACHINE
(
FROM
PHY
T
EST
S
PECIFICATION
)
1.
Enable the DUT to enter the Polling.Active state by sending TS1 with PAD (K23.7).
2.
The DUT will go into the Polling.Configuration state after sending more than 1024 TS1 and 8
consecutive TS1 or TS2 with Pad or Loopback bit asserted have been received.
3.
The DUT will next enter the Configuration state after 8 consecutive TS2 with PAD have been
received and 16 TS2 have been transmitted after 1 TS2 has been received.
4.
Start speed negotiation by sending TS1 at 2.5 GT/s advertising the supported speeds.
Electrical idle for more than 1 ms allows the product to adjust to the requested speed unless
the requested speed is 2.5 GT/s.
5.
The DUT will finally switch to the Loopback mode after having two consecutive TS1 at the
requested speed with Loopback bit asserted.
