GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 42 of 123
2.
Using coaxial cables, connect the MU181500B sub-rate clock outputs to the Ref Clk+/- of the
CBB.
3.
Using a SMA cable, connect a MU195020A/MU196020A Aux Out connector to an Aux input on
the oscilloscope.
Note the other unused MU195020A/MU196020A Aux Out connector must be
terminated with the J1632A coaxial terminator due to differential signal output (not shown in
above setup).
4.
Using phase matched cables, connect Channels 1 and 3 on the oscilloscope to the pick-off tee
input ports.
5.
Using coaxial cables, connect the CBB Tx Lane to the pick-off tee tapped input ports.
6.
Using coaxial cables, connect the pick-off tee outputs to the MU195040A data inputs for
loopback error detection.
7.
Using the J1627A GND connection cable, connect the CBB to ground.
5.6
Set Up Automated DUT Rx Compliance Test
After link EQ testing has successfully completed from previous section, proceed with testing for
DUT Rx compliance with the following setup.
5.6.1
Connect Equipment for System Board Rx Compliance Testing
The following Rx compliance test setup uses a PCI-SIG compliance load board (CLB) test fixture for
the PCIe Gen 5 System Board DUT.
Note
: Use logical Lane 0 for the following test setup.
