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3-4-3
Output OFF Bit
SR bit 25215 is turned ON to turn OFF all outputs from the PC. The OUT
INHB. indicator on the front panel of the CPU will light. When the Output OFF
Bit is OFF, all output bits will be refreshed in the usual way.
The status of the Output OFF bit is maintained for power interruptions or
when PC operation is stopped.
3-4-4
FAL (Failure Alarm) Area
A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or
FALS instruction is executed. These codes are user defined for use in error
diagnosis, although the PC also outputs FAL codes to these bits, such as one
caused by battery voltage drop.
This area can be reset by executing the FAL instruction with an operand of
00 or by performing a Failure Read Operation from the Programming Con-
sole.
3-4-5
Low Battery Flag
SR bit 25308 turns ON if the voltage of the CPU or File Memory backup bat-
tery drops. The warning indicator on the front of the CPU will also light.
This bit can be programmed to activate an external warning for a low battery
voltage.
3-4-6
Cycle Time Error Flag
SR bit 25309 turns ON if the cycle time exceeds 100 ms. The warning indica-
tor on the front of the CPU will also light. Program execution will not stop,
however, unless the maximum time limit set for the watchdog timer is ex-
ceeded. Timing may become inaccurate after the cycle time exceeds 100 ms.
3-4-7
I/O Verification Error Flag
SR bit 25310 turns ON when the Units mounted in the system disagree with
the I/O table registered in the CPU. The warning indicator on the front of the
CPU also lights, but PC operation will continue.
To ensure proper operation, PC operation should be stopped, Units checked,
and the I/O table corrected whenever this flag goes ON.
3-4-8
First Cycle Flag
SR bit 25315 turns ON when PC operation begins and then turns OFF after
one cycle of the program. The First Cycle Flag is useful in initializing counter
values and other operations. An example of this is provided in
5-11 Timer
and Counter Instructions
.
3-4-9
Clock Pulse Bits
Five clock pulses are available to control program timing. Each clock pulse
bit is ON for the first half of the rated pulse time, then OFF for the second
half. In other words, each clock pulse has a duty factor of 50%.
SR Area
Section 3-4