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TABLE OF CONTENTS

SECTION 1
Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2

Relay Circuits: The Roots of PC Logic

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1-3

PC Terminology

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4

OMRON Product Terminology

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5

Overview of PC Operation

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1-6

Peripheral Devices

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1-7

Available Manuals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 2
Hardware Considerations

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2-1

Indicators

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2-2

PC Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 3
Memory Areas

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2

Data Area Structure

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3-3

IR (Internal Relay)Area

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3-4

SR (Special Relay) Area

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3-5

AR (Auxiliary Relay) Area

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3-6

DM (Data Memory) Area

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3-7

HR (Holding Relay) Area

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8

TC (Timer/Counter) Area

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-9

LR (Link Relay) Area

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3-10 Program Memory

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3-11 File Memory

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3-12 Trace Memory

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3-13 TR (Temporary Relay) Area

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SECTION 4
Writing and Inputting the Program

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4-1

Basic Procedure

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4-2

Instruction Terminology

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3

Basic Ladder Diagrams

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4-4

The Programming Console

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5

Preparation for Operation

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4-6

Inputting, Modifying, and Checking the Program

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7

Controlling Bit Status

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4-8

Work Bits (Internal Relays)

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4-9

Programming Precautions

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4-10 Program Execution

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Summary of Contents for SYSMAC C1000H

Page 1: ...Cat No W140 E1 04 Programmable Controllers SYSMAC C1000H C2000H...

Page 2: ...C1000H C2000H Programmable Controllers Operation Manual Revised May 2003...

Page 3: ...iv...

Page 4: ...means word and is abbreviated Wd in documentation The abbreviation PC means Programmable Controller and is not used as an abbreviation for any thing else Visual Aids The following headings appear in t...

Page 5: ...vi...

Page 6: ...Special Relay Area 23 3 5 AR Auxiliary Relay Area 31 3 6 DM Data Memory Area 36 3 7 HR Holding Relay Area 37 3 8 TC Timer Counter Area 37 3 9 LR Link Relay Area 38 3 10 Program Memory 39 3 11 File Mem...

Page 7: ...a Conversion 148 5 17 BCD Calculations 158 5 18 Binary Calculations 174 5 19 Logic Instructions 179 5 20 Subroutines and Interrupt Control 182 5 21 Block Programming Instructions 190 5 22 Step Instruc...

Page 8: ...s 286 8 5 Error Flags 289 8 6 Troubleshooting 290 Appendices 293 A Standard Models 293 B Programming Instructions 303 C Programming Console Operations 335 D Error and Arithmetic Flag Operation 349 E D...

Page 9: ...the basic terms used in ladder diagram programming It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs Descriptions of per...

Page 10: ...manual may result in personal injury or death damage to the product or product failure Please read each section in its entirety and be sure you understand the information provided in the section and r...

Page 11: ...erating a PC and ex plains basic terminology used with OMRON PCs Descriptions of peripheral devices used with the C1000H and C2000H and a table of other manuals available to use with this manual for s...

Page 12: ...does the PC know when to activate each pusher Much more complicated operations however are also possible The problem is how to get the desired control signals from available inputs at appropriate time...

Page 13: ...nters the PC through terminals or through pins on a connector on a Unit The place where a signal enters the PC is called an input point This input point is allocated a location in memory that reflects...

Page 14: ...view of PC Operation The following are the basic steps involved in programming and operating a C1000H or C2000H Assuming you have already purchased one or more of these PCs you must have a reasonable...

Page 15: ...e operations Identify the physical relationships be tween the I O devices as well as the kinds of responses that should occur between them For instance a photoelectric switch might be functionally tie...

Page 16: ...ing an Optical Host Link Unit also enables the use of optical fiber cable to connect the FIT to the PC Wired Host Link Units are available when desired Although FIT does not have optical connectors co...

Page 17: ...er PROM Writer Operation Guide W155 Procedures for writing programs to EPROM chips Floppy Disk Interface Unit Operation Guide W119 Procedures for interfacing a PC to a floppy disk drive Wired Remote I...

Page 18: ...ects of the C1000H and C2000H that are relevant to programming and software operation These include indicators on the CPU and Duplex Unit and basic PC configuration This information is covered in deta...

Page 19: ...0H Indicator Function POWER Lights when power is supplied to the CPU RUN Lights when the CPU is operating normally ERR Lights when an error is discovered in error diagnosis operations When this indica...

Page 20: ...U Indicate which CPU is active CPU RUN Lights whenever the RUN indicators on the CPUs are lit WAITING Lights at the beginning of duplex operation until the programs have been verified 1 to 20 seconds...

Page 21: ...Us is active and the other is on standby as long as both are operating normally Both CPUs must contain the same size and type of Memory Unit and the same program If the active CPU fails to operate nor...

Page 22: ...ry Units and all other Link Units must be mounted only to certain slots on specific Racks All Units occupy only one slot except for the PID Unit and some Position Control Units All Units that do not r...

Page 23: ...4 2 Data Retention Control Bit 28 3 4 3 Output OFF Bit 29 3 4 4 FAL Failure Alarm Area 29 3 4 5 Low Battery Flag 29 3 4 6 Cycle Time Error Flag 29 3 4 7 I O Verification Error Flag 29 3 4 8 First Cycl...

Page 24: ...in a File Memory Unit mounted to the CPU Rack and used to store programs or data Trace Memory TM TM Traces of 250 instructions Used to store results from traces of program execution When some bits and...

Page 25: ...13 12 11 10 09 08 07 06 05 04 03 02 01 00 The DM area is accessible by word only you cannot designate an individual bit within a DM word Data in the IR SR HR AR and LR areas is accessible either by wo...

Page 26: ...nding decimal digit The BCD bits 0101011101010111 are converted to decimal by considering each four bits from the right Binary 0101 is deci mal 5 binary 0111 is decimal 7 The decimal equivalent would...

Page 27: ...be used in instructions that control bit status e g the OUTPUT DIF FERENTIATE UP and KEEP instructions Output bits are used to output program execution results and can be used in any order in programm...

Page 28: ...I O Master Unit None Remote I O Slave Unit None I O Link Unit 1 or 2 words File Memory Unit None Position Control Units 2 or 4 words I O Control Unit None ID Sensor Unit 5 words Remote I O Systems ar...

Page 29: ...ster Unit called a Master for short mounted to a Rack and any Remote I O Slave Units connected to it are not allocated I O words any Units on the Slave Racks or other Remote I O Units connected to the...

Page 30: ...rds allocated to any one slot changes all word allocations past that slot will also change requiring that the program be changed to allow for this Sometimes program changes can be avoided when a Unit...

Page 31: ...hese bits not assigned specific functions should be left OFF Bits in words SR 237 through SR 251 only can be used as work bits if the Systems for which these bits are dedicated are not used by the PC...

Page 32: ...rol bits are used when Link Units such as PC Link Units SYSMAC LINK Units Remote I O Units SYSMAC NET Link Units or Host Link Units are mounted to the PC Racks or to the CPU For additional information...

Page 33: ...to restart a Host Link Unit SR bits used with Host Link Sys tems are summarized in the following table Rack mounting Host Link Unit Restart bits are not effective for the Multilevel Rack mounting Hos...

Page 34: ...SR 245 for the SYSMAC LINK System the status of SW3 4 on the SYSMAC NET Link Unit determines the words used for operating level 1 of the SYSMAC NET Link System i e if SW3 4 is ON SR 242 through SR 245...

Page 35: ...PC Link System or a Multilevel PC Link System Refer to the PC Link System Manual for details Error and Run Flag bit assignments are described below Bits 00 through 07 of each word are the Run flags wh...

Page 36: ...level 1 Unit 12 level 0 Unit 4 level 0 13 Unit 13 level 1 Unit 5 level 1 Unit 13 level 0 Unit 5 level 0 14 Unit 14 level 1 Unit 6 level 1 Unit 14 level 0 Unit 6 level 0 15 Unit 15 level 1 Unit 7 leve...

Page 37: ...oltage 3 4 6 Cycle Time Error Flag SR bit 25309 turns ON if the cycle time exceeds 100 ms The warning indica tor on the front of the CPU will also light Program execution will not stop however unless...

Page 38: ...11 Duplex System Flags Five flags are provided in the SR area to monitor Duplex System operation These flags are used only with a C2000H Duplex System The following table summarizes Duplex System fla...

Page 39: ...ult of a comparison shows two operands to be equal or when the result of an arithmetic operation is zero SR bit 25507 turns ON when the result of a comparison shows the second of two operands to be le...

Page 40: ...Link System operating level 1 service time per cycle 18 12 Trace Complete Flag 13 Tracing Flag 14 Trace Start Bit 15 Sampling Start Bit 19 00 File Memory Unit Error Reset Bit 01 FM Data Transfer Flag...

Page 41: ...tion can be set to occur either according to settings from a Peripheral Device e g FIT or automatically in the LR and or DM areas If automatic allocation is designated the number of words to be alloc...

Page 42: ...le when a SYSMAC LINK Unit and or SYSMAC NET Link Unit is mounted to a Rack These times are recorded in 4 digit BCD to tenths of a millisecond 000 0 ms to 999 9 ms and are refreshed every cycle Bits 1...

Page 43: ...1910 500 to 749 AR 1911 750 to 999 AR 1912 1000 to 1249 AR 1913 1250 to 1499 AR 1914 1500 to 1749 AR 1915 1750 to 1999 The FM Blocks Counter AR 20 indicates the number of the block that is cur rently...

Page 44: ...directly to the CPU This in cludes CPU mounting Host Link Units Programming Consoles and Interface Units This flag is refreshed every cycle 3 5 11 FALS generating Address AR 2400 to AR 2403 and AR 25...

Page 45: ...24 Indirect address 3 7 HR Holding Relay Area The HR area is used to store manipulate various kinds of data and can be accessed either by word or by bit Word addresses range from HR 00 through HR 99 b...

Page 46: ...er ruptions The PVs of timers are reset when PC operation is begun and when reset in interlocked program sections Refer to 5 7 Interlock and Interlock Clear IL 02 and ILC 03 for details on timer and c...

Page 47: ...a File Memory Unit is mounted to the PC This area contained in RAM within the File Memory Unit can be used for data storage and retrieval Program Memory and or IR SR DM LR HR AR and TC area data can b...

Page 48: ...Keyboard 58 4 4 2 PC Modes 59 4 4 3 The Display Message Switch 61 4 5 Preparation for Operation 61 4 5 1 Entering the Password 61 4 5 2 Clearing Memory 62 4 5 3 Registering the I O Table 64 4 5 4 Clea...

Page 49: ...The basics of ladder diagram programming and conversion to mnemonic code are described in 4 3 Basic Ladder Diagrams Preparing for and input ting the program via the Programming Console are described i...

Page 50: ...instruction The number above each condition indicates the operand bit for the instruction It is the status of the bit associated with each condition that determines the execution condition for followi...

Page 51: ...re to be input in mne monic code 4 3 2 Mnemonic Code The ladder diagram cannot be directly input into the PC via a Programming Console a GPC a FIT or LSS is required To input from a Programming Consol...

Page 52: ...able are filled in for the instruction word only For all other lines the left two columns are left blank If the instruction requires no definer or bit operand the operand col umn is left blank for fir...

Page 53: ...Instruction Address Instruction Operands 00000 LD 00000 00001 AND NOT 00100 00002 AND LR 0000 00003 Instruction The instruction would have an ON execution condition only when all three conditions are...

Page 54: ...of the operand bit The following is one example Study this example until you are convinced that the mnemonic code follows the same logic flow as the ladder diagram Instruction 00002 00003 00000 00001...

Page 55: ...t points assigned IR 00000 and IR 00001 are controlling the output points as signed IR 00200 and IR 00201 respectively The length of time that a bit is ON or OFF can be controlled by combining the OUT...

Page 56: ...emonic code using AND and OR instructions alone If an AND between IR 00002 and the results of an OR between IR 00000 and IR 00001 is attempted the OR NOT between IR 00002 and IR 00003 is lost and the...

Page 57: ...0002 00003 AND 00003 00004 OR LD Naturally some diagrams will require both AND LOAD and OR LOAD instruc tions To code diagrams with logic block instructions in series the diagram must be divided into...

Page 58: ...02 00003 00040 00005 00501 The first of each pair of conditions is converted to LOAD with the assigned bit operand and then ANDed with the other condition The first two blocks can be coded first follo...

Page 59: ...ia gram below cannot be coded without separating it into two blocks combined with OR LOAD In this example the three blocks have been coded first and then OR LOAD has been used to combine the last two...

Page 60: ...rmed These blocks are then coded combining the small blocks first and then combining the larger blocks Either AND LOAD or OR LOAD is used to combine the blocks i e AND LOAD or OR LOAD always combines...

Page 61: ...OR LD 00010 AND LD 00011 OUT 00503 The following type of diagram can be coded easily if each block is coded in order first top to bottom and then left to right In the following diagram blocks a and b...

Page 62: ...xecute as written this diagram could be drawn as shown below to eliminate the need for the first OR LOAD and the AND LOAD simplifying the program and saving memory space 00002 00003 LR 0000 00001 0000...

Page 63: ...ram can be redrawn as follows to simplify program structure and coding and to save memory space 00006 00007 LR 0000 00005 00001 00002 00003 00004 00000 Address Instruction Operands 00000 LD 00006 0000...

Page 64: ...00 AND 00001 OR 00500 AND 00002 AND NOT 00003 LD 01000 AND 01001 OR 00006 LD 00004 AND 00005 AND LD Address Instruction Operands 00000 LD 00000 00001 AND 00001 00002 LD 01000 00003 AND 01001 00004 OR...

Page 65: ...ges to data in memory areas will not be possible unless connected to the active CPU 4 4 1 The Keyboard The keyboard of the Programming Console is functionally divided by key color into the following f...

Page 66: ...put bit Pressed to enter OUT the Output instruction or used with NOT to enter OUT NOT Also pressed to indicate an output bit Pressed to enter TIM the Timer instruction or to designate a TC number that...

Page 67: ...and thus the controlled system When the PC is turned on the mode it will be in is affected by any peripheral device connected or mounted to the CPU as follows 1 2 3 1 No Peripheral Device Connected W...

Page 68: ...rm that all wiring for the PC has been installed and checked prop erly 2 Confirm that a RAM Unit is mounted as the Memory Unit and that the write protect switch is OFF 3 Connect the Programming Consol...

Page 69: ...pecified the clear operation will clear all of the above memory areas pro vided that the Memory Unit attached to the PC is a RAM Unit or an EEPROM Unit and the write enable switch is ON If the write e...

Page 70: ...ate key after entering REC RESET HR is pressed to designate both the HR and AR areas In other words specifying that HR is to be re tained will ensure that AR is retained also If not specified for rete...

Page 71: ...registered when ever I O Units are changed Note If I OTBL WRIT DISABLED is displayed the I O table cannot be written Check the number of Remote I O Units duplicate word settings for Optical I O Units...

Page 72: ...ng the I O table The same word multiplier can be assigned to more than one Master in the same system as long as the same word is not allocated to more than one unit Word allocations to I O Link Units...

Page 73: ...RIT I O CHECK G 00000I OTBL WRIT 1 7U RMT0 00000I OTBL WRIT 1 7U RMT0 0 00000I OTBL WRIT 2 3U RMT1 00000I OTBL WRIT 2 4U RMT22 00000I OTBL WRIT OK 00000I OTBL WRIT 1 7U RMT0 4 5 4 Clearing Error Messa...

Page 74: ...program memory The I O Table Transfer operation will not work if 1 2 3 1 When the memory unit is not RAM or 2 When the contents of program memory exceeds 31 7K words To find out the capacity of progra...

Page 75: ...ally mounted units Disregard this error message This message will not be displayed for word reservations 3 see below Dummy I O table entries can be made for Input Units use the 1 key Output Units use...

Page 76: ...Units while the CPU is operating Only 16 32 and 64 point I O Units can be changed on line On line changes are not possible on Racks containing Inter rupt Input Units Special I O Units or Remote I O U...

Page 77: ...0 10001 00000I OTBLEXCHG 0 1U 0 001 00000I OTBLEXCHG 0 1U 0 001 00000 UNIT XCHG 0 1U 0 001 00000 EXCHG END 0 1U 0 001 00000I OTBLEXCHG 0 1U 0 001 The outputs of the I O Unit will turn ON for an instan...

Page 78: ...00000I OTBL VER OK 00000I OTBL VER 0 1U O I Meaning of Displays Duplication Indicates a Remote I O Unit that has not been registered 00000I OTBL VER R I R W 00000I OTBL VER U RMT 4 5 9 Reading the I...

Page 79: ...2 Rack 3 Rack 4 Rack 5 Rack 6 Rack 7 Expansion I O Racks Expansion I O Racks Slot number 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 In Duplex System CPU Rack or CPU I O Rack Key Sequence 0 to 7 0 to 9 Rack numbe...

Page 80: ...0 5U 00000I OTBL READ 0 5U I 005 00000I OTBL READ 0 4U I 004 00000I OTBL READ 0 5U I 005 Meaning of Displays I O Unit Designations for Displays No of points 16 32 64 Input Unit Output Unit I O Units...

Page 81: ...Remote I O Master Unit number 0 to 7 Indicates a Remote I O Rack 00000I OTBL READ R U Interrupt Units Interrupt Input Unit number 00000I OTBL READ 1 5U IN Optical I O Units I O Link Units Remote Termi...

Page 82: ...correct it as required Further debugging methods are provided in Section 7 Debugging and Execution 4 6 1 Setting and Reading from Program Memory Address When inputting a program for the first time it...

Page 83: ...he next display will appear If the instruction requires two or more words the next display will indicate the next operand required and provide a default value for it If the instruction requires only o...

Page 84: ...re always written between pointed parentheses like this Both types of function code are used in basically the same way but SHIFT must be pressed before inputting a block instruction function code To d...

Page 85: ...D NOP 00 00202 FUN 00202 TIMH 15 001 00202 TIMH DATA 0000 00202 TIMH 0500 00203READ NOP 00 Address Instruction Operands 00200 LD 00002 00201 TIM 000 0123 00202 TIMH 15 001 0500 The following error mes...

Page 86: ...indicate the desired check level see below When the check level is en tered the program check will start If an error is discovered the check will stop and a display indicating the error will appear Pr...

Page 87: ...and so that ELSE 03 when used is located between them LOOP LEND ERR LOOP 09 LEND 10 and LOOP 10 NOT have not been used properly Correct the program so that loops are not nested do not interrupt any IF...

Page 88: ...the Cycle Time Once the program has been cleared of syntax errors the cycle time should be checked This is possible only in RUN or MONITOR mode while the pro gram is being executed See Section 6 Prog...

Page 89: ...when inputting the pro gram and press SRCH Once an occurrence of an instruction or bit address has been found any additional occurrences of the same instruction or bit can be found by pressing SRCH ag...

Page 90: ...an be de leted or another instruction can be inserted before it These are not possible in RUN or MONITOR modes To insert an instruction display the instruction before which you want the new instructio...

Page 91: ...k addresses or no unaddressed instructions The following mnemonic code shows the changes that are achieved in a pro gram through the key sequences and displays shown below Original Program Address Ins...

Page 92: ...00005 AND 00103 00006 AND 00105 00007 AND NOT 00104 00008 OUT 00201 00009 END 01 Find the instruction that requires deletion Confirm that this is the instruction to be deleted Program After Deletion D...

Page 93: ...the branch ing point cannot be changed before returning to the branch line instructions at the far right do not change the execution condition then the branch line will be executed correctly and no s...

Page 94: ...ands 00000 LD 00000 00001 OUT TR 0 00002 AND 00001 00003 OUT TR 1 00004 AND 00002 00005 OUT 00500 00006 LD TR 1 00007 AND 00003 00008 OUT 00501 00009 LD TR 0 00010 AND 00004 00011 OUT 00502 00012 LD T...

Page 95: ...on 2 00003 TR 0 00001 00004 00002 00001 00003 00000 00004 00002 00001 Instruction 1 Instruction 2 Note TR bits are only used when programming using mnemonic code They are not necessary when inputting...

Page 96: ...that of IR 00002 would determine the execution conditions for in structions 1 and 2 respectively Because IR 00000 is ON this would produce the same results as ANDing the status of each of these bits...

Page 97: ...once i e each of these numbers can be used once in a JUMP instruction and once in a JUMP END instruction When a JUMP instruction assigned one of these numbers is executed execution moves immediately t...

Page 98: ...f this diagram would differ from that of the diagram described above e g in the previous diagram interlocks would reset certain parts of the interlocked section however jumps do not affect the status...

Page 99: ...uire only one line of mnemonic code 00000 00001 DIFU 13 00200 DIFD 14 00201 Address Instruction Operands 00000 LD 00000 00001 DIFU 13 00200 Address Instruction Operands 00000 LD 00001 00001 DIFD 14 00...

Page 100: ...erlocked program section when the execution condition for the INTERLOCK instruction was ON Here just as in the same diagram using the KEEP in struction two reset bits are used i e HR 0000 can be turne...

Page 101: ...ork bits Under standing the use of these bits is essential to effective programming Work bits can be used to simplify programming when a certain combination of conditions is repeatedly used in combina...

Page 102: ...00005 AND NOT 00003 00006 OR LD 00007 LD 00004 00008 AND NOT 00005 00009 OR LD 00010 OUT 00100 4 9 Programming Precautions The number of conditions that can be used in series or parallel is unlimited...

Page 103: ...RLOCK CLEAR JUMP END and step instructions Each of these instructions is used as the second of a pair of instructions and is controlled by the execution condition of the first of the pair Conditions s...

Page 104: ...e desired data is moved to a word before that word is used as the operand for an instruction Remember that an in struction line is completed to the terminal instruction at the right before exe cuting...

Page 105: ...instructions as well The OUTPUT instructions used in examples in this manual can therefore generally be re placed by other instructions to modify the program for specific applications other than contr...

Page 106: ...C 41 159 5 17 5 BCD ADD ADD 30 160 5 17 6 DOUBLE BCD ADD ADDL 54 161 5 17 7 BCD SUBTRACT SUB 31 162 5 17 8 DOUBLE BCD SUBTRACT SUBL 55 164 5 17 9 BCD MULTIPLY MUL 32 165 5 17 10 DOUBLE BCD MULTIPLY MU...

Page 107: ...EP 08 SNXT 09 199 5 23 Special Instructions 208 5 23 1 FAILURE ALARM FAL 06 and SEVERE FAILURE ALARM FALS 07 208 5 23 2 DISPLAY MESSAGE MSG 46 209 5 23 3 BIT COUNTER BCNT 67 210 5 23 4 WATCHDOG TIMER...

Page 108: ...m Memory The first word is the instruction word which specifies the instruction and contains any definers described below or operand bits required by the instruction Other operands required by the ins...

Page 109: ...ion When the DM area is specified for an operand an indirect address can be used Indirect DM addressing is specified by placing an asterisk before the DM DM When an indirect DM address is specified th...

Page 110: ...0 to DM 0000 only once after 00000 goes ON Even if 00000 remains ON for 2 0 seconds with the same 80 ms cycle time the move operation will be exe cuted only during the first cycle in which 00000 has c...

Page 111: ...ough any blank data col umn spaces for all instruction words that do not require data so that the data column can be quickly scanned to see if any addresses have been left out If an IR or SR address i...

Page 112: ...014 LD TIM 000 00015 MOV 21 HR 00 LR 00 00016 LD HR 0015 00017 OUT NOT 00500 00100 00200 DIFU 13 22500 00500 BCNT 67 0001 004 HR 00 MOV 21 HR 00 LR 00 01001 01002 LR 6300 TIM 000 22500 00002 00005 HR...

Page 113: ...es one instruction and each of the block instruction lines requires one word i e one line in the mnemonic code table Operand bits operand words and definers for block instruction are also coded in the...

Page 114: ...other instruc tions Each of these instructions and each bit address can be used as many times as required Each can be used in as many of these instructions as re quired The status of the bit operand B...

Page 115: ...ctions required a basic understanding of logic block instructions is required For an introduction to logic blocks refer to 4 2 3 Logic Block Instructions For details and exam ples refer to 7 1 3 Logic...

Page 116: ...B B Bit IR AR HR LR DIFD 14 B Any output bit can generally be used in only one instruction that controls its status Refer to 3 2 IR Area for details and to 5 20 Block Instructions for in formation on...

Page 117: ...each cycle if the content of one or both operands change Diagram B however is an ex ample of how DIFU 13 can be used to ensure that CMP 20 is executed only once each time the desired execution condit...

Page 118: ...11 bit status is shown below S execution condition R execution condition Status of B KEEP 11 operates like the self maintaining bit described in 4 7 3 Self main taining Bits Seal The following two di...

Page 119: ...00002 00001 OR 00003 00002 OR 00004 00003 LD 00005 00004 KEEP 11 HR 0000 00005 LD HR 0000 00006 OUT 00500 S R KEEP 11 HR 0000 KEEP 11 can also be combined with TIM to produce delays in turning bits O...

Page 120: ...ve i e before the interlock condition for IL 02 went OFF The ladder diagram and bit status changes for this are shown below The interlock is in effect while 00000 is OFF Notice that 01000 is not turne...

Page 121: ...Jump numbers 01 through 99 may be used only once in JMP 04 and once in JME 05 i e each can be used to define one jump only Jump number 00 can be used as many times as desired JMP 04 is always used in...

Page 122: ...f a bit is turned ON by DIFU 13 or DIFD 14 and then a jump is made in the next cycle so that DIFU 13 or DIFD 14 are skipped the designated bit will re main ON until the next time the execution conditi...

Page 123: ...ruction that was used to define the counter TC numbers can be designated as operands that require either bit or word data When designated as an operand that requires bit data the TC number accesses a...

Page 124: ...n for TIM and the Completion Flag assigned to it Execution condition Completion Flag ON OFF ON OFF SV SV Timers in interlocked program sections are reset when the execution condi tion for IL 02 is OFF...

Page 125: ...M 001 00003 TIM 002 9000 00004 LD TIM 002 00005 OUT 00200 TIM 001 9000 TIM 002 9000 900 0 s 900 0 s In this example 00200 will be turned ON 30 minutes after 00000 goes ON TIM can also be combined with...

Page 126: ...When TIM 001 comes ON i e when the SV of TIM 001 has expired 00204 will be turned OFF through TIM 001 i e TIM 001 will turn ON which as a normally closed condition creates an OFF execution condition...

Page 127: ...lock pulse is used 25502 so that 00206 would be turned ON and OFF every second i e it would be ON for 0 5 seconds and OFF for 0 5 seconds Precise timing and the initial status of 00206 would depend on...

Page 128: ...the DM area boundary has been exceeded 5 12 3 COUNTER CNT N TC number 000 through 511 Ladder Symbol Definer Values SV Set value word BCD IR AR DM HR LR Operand Data Areas CP R CNT N SV Each TC number...

Page 129: ...s zero 00205 will be turned ON 00000 CP R CNT 004 0150 00002 00001 00205 CNT 004 Address Instruction Operands 00000 LD 00000 00001 AND 00001 00002 LD 00002 00003 CNT 004 0150 00004 LD CNT 004 00005 OU...

Page 130: ...00001 00002 LD NOT 00002 00003 OR CNT 001 00004 OR CNT 002 00005 CNT 001 0100 00006 LD CNT 001 00007 LD NOT 00002 00008 CNT 002 0200 00009 LD CNT 002 00010 OUT 00203 CNT can be used in sequence as man...

Page 131: ...T 001 0700 00000 25502 00001 CNT 001 00202 Address Instruction Operands 00000 LD 00000 00001 AND 25502 00002 LD NOT 00001 00003 CNT 001 0700 00004 LD CNT 001 00005 OUT 00202 Caution The shorter clock...

Page 132: ...remented again CNTR 12 is reset with a reset input R When R goes from OFF to ON the PV is reset to zero The PV will not be incremented or decremented while R is ON Counting will begin again when R goe...

Page 133: ...ion P is ON and was OFF the last execution and 2 R is OFF then execution condition I is shifted into the rightmost bit of a shift register defined between St and E i e if I is ON a 1 is shifted into t...

Page 134: ...R 00 AR 01 00005 LD 00004 00006 DIFU 13 12800 00007 LD 12800 00008 JMP 04 00 00009 LD 12800 00010 OUT AR 0100 00011 JME 05 00 When a bit that is part of a shift register is used in OUT or any other in...

Page 135: ...R 0003 00002 HR 0003 00500 Address Instruction Operands 5 13 2 REVERSIBLE SHIFT REGISTER SFTR 84 C Control word IR AR DM HR LR St Starting word IR AR DM HR LR Ladder Symbols Operand Data Areas E End w...

Page 136: ...condition as long as the reset bit is OFF and as long as bit 14 is ON If SFTR 84 is executed with an OFF execution condition or if SFTR 84 is executed with bit 14 OFF the shift register will remain un...

Page 137: ...Status to input Shift pulse Reset SFTR 84 050 LR 20 LR 21 5 13 3 ARITHMETIC SHIFT LEFT ASL 25 Wd Shift word IR AR DM HR LR Ladder Symbols Operand Data Areas ASL 25 Wd ASL 25 Wd When the execution con...

Page 138: ...LEFT ROL 27 Wd Rotate word IR AR DM HR LR Ladder Symbols Operand Data Areas ROL 27 Wd ROL 27 Wd When the execution condition is OFF ROL 27 is not executed When the execution condition is ON ROL 27 sh...

Page 139: ...n existent Content of DM word is not BCD or the DM area boundary has been exceeded CY Receives the data of bit 15 EQ ON when the content of Wd is 0 otherwise OFF 5 13 7 ONE DIGIT SHIFT LEFT SLD 74 Lad...

Page 140: ...is not executed When the execution condition is ON SRD 75 shifts data between St and E inclusive by one digit four bits to the right 0 is written into the leftmost digit of St and the rightmost digit...

Page 141: ...ilizing all of the data areas of the PC Effective communica tions in Link Systems also requires data movement All of these instructions change only the content of the words to which data is being move...

Page 142: ...ed ON Source word Destination word Bit status inverted TC numbers cannot be designated as D to change the PV of the timer or counter However these can be easily changed using BSET 71 ER Indirectly add...

Page 143: ...ord is non existent Content of DM word is not BCD or the DM area boundary has been exceeded The following example shows how to use BSET 71 to change the PV of a timer depending on the status of IR 000...

Page 144: ...the contents of S S 1 S N to D D 1 D N 2 D 3 4 5 1 D 1 3 4 5 2 D 2 3 4 2 2 D N 6 4 5 2 S 3 4 5 1 S 1 3 4 5 2 S 2 3 4 2 2 S N 6 4 5 ER N is not BCD S and S N or D and D N are not in the same data area...

Page 145: ...hen the execution condition is OFF DIST 80 is not executed When the execution condition is ON DIST 80 copies the content of S to DBs Of i e Of is added to DBs to determine the destination word 2 DBs O...

Page 146: ...S Bi D MOVB 82 S Bi D Limitations The rightmost two digits and the leftmost two digits of Bi must each be be tween 00 and 15 When the execution condition is OFF MOVB 82 is not executed When the execu...

Page 147: ...shown below Digits from S will be copied to consecutive digits in D starting from the desig nated first digit and continued for the designated number of digits If the last digit is reached in either S...

Page 148: ...t to the GR EQ and LE flags in the SR area Placing other instructions between CMP 20 and the operation which ac cesses the EQ LE and GR flags may change the status of these flags Be sure to access the...

Page 149: ...example uses TIM CMP 20 and the LE flag 25507 to pro duce outputs at particular times in the timer s countdown The timer is started by turning ON 00000 When 00000 is OFF TIM 010 is reset and the secon...

Page 150: ...5507 TIM 010 Output at 100 s Output at 200 s Output at 300 s Output at 500 s Address Instruction Operands Address Instruction Operands 00000 LD 00000 00001 TIM 010 5000 00002 CMP 20 TIM 010 4000 00003...

Page 151: ...n any of these ranges inclu sive of the upper and lower limits the corresponding bit in R is set The comparisons that are made and the corresponding bit in R that is set for each true comparison are s...

Page 152: ...01 which contains 0210 with the given ranges Address Instruction Operands 00000 LD 00000 00001 BCMP 68 001 HR 10 HR 05 5 15 3 TABLE COMPARE TCMP 85 CD Compare data IR SR AR DM HR TC LR TB First compar...

Page 153: ...3 0400 HR 0503 0 HR 14 0500 HR 0504 0 HR 15 0600 HR 0505 0 HR 16 0210 HR 0506 1 HR 17 0800 HR 0507 0 HR 18 0900 HR 0508 0 HR 19 1000 HR 0509 0 HR 20 0210 HR 0510 1 HR 21 1200 HR 0511 0 HR 22 1300 HR 0...

Page 154: ...execution condition is ON BIN 23 converts the BCD content of S into the numerically equivalent binary bits and outputs the binary value to R Only the content of R is changed the content of S is left u...

Page 155: ...4 will not be executed When the instruction is not executed the content of R remains unchanged BCD 24 converts the binary hexadecimal content of S into the numerically equivalent BCD bits and outputs...

Page 156: ...is non existent Content of DM word is not BCD or the DM area boundary has been exceeded EQ ON when 0 is placed in R 5 16 5 4 TO 16 DECODER MLPX 76 S Source word IR SR AR DM HR TC LR Di Digit designato...

Page 157: ...r of digits to be converted must be in the same data area as R e g if two digits are converted the last word address in a data area cannot be designated if three digits are converted the last two word...

Page 158: ...11 0 DM 12 0 20 HR 1012 0 HR 1112 0 HR 1212 0 DM 13 0 21 3 HR 1013 0 HR 1113 0 HR 1213 0 DM 14 0 22 HR 1014 0 HR 1114 0 HR 1214 0 DM 15 0 23 HR 1015 1 HR 1115 0 HR 1215 0 15 6 0 Not Converted 5 16 6 1...

Page 159: ...data area as SB The digits of Di are set as shown below Specifies the first digit to receive converted data 0 to 3 Number of words to be converted 0 to 3 0 1 word 1 2 words 2 3 words 3 4 words Not use...

Page 160: ...0 00001 DMPX 77 010 HR 20 0010 00002 DMPX 77 LR 10 HR 20 0012 5 16 7 7 SEGMENT DECODER SDEC 78 S Source word binary IR SR AR DM HR TC LR Di Digit designator IR AR DM HR TC LR Ladder Symbols Operand Da...

Page 161: ...ceive converted data 0 to 3 Number of digits to be converted 0 to 3 0 1 digit 1 2 digits 2 3 digits 3 4 digits First half of D to be used 0 Rightmost 8 bits 1st half 1 Leftmost 8 bits 2nd half Not use...

Page 162: ...Bits g f e d c b a 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 2 0 0 1 0 0 1 0 1 1 0 1 1 3 0 0 1 1 0 1 0 0 1 1 1 1 4 0 1 0 0 0 1 1 0 0 1 1 0 5 0 1 0 1 0 1 1 0 1 1 0 1 6 0 1 1 0 0 1 1 1 1 1 0 1...

Page 163: ...umber of digits to be converted and the half of D to receive the first ASCII code rightmost or leftmost 8 bits are designated in Di If multiple digits are designated they will be placed in order start...

Page 164: ...e ASCII code When odd parity is designated the leftmost bit of each ASCII character will be adjusted so that there is an odd number of ON bits ER Incorrect digit designator or data area for destinatio...

Page 165: ...exceeded EQ ON when the incremented result is 0 5 17 2 DECREMENT DEC 39 Wd Decrement word BCD IR AR DM HR LR Ladder Symbols Operand Data Areas DEC 39 Wd DEC 39 Wd When the execution condition is OFF D...

Page 166: ...rry in the result EQ ON when the result is 0 If 00002 is ON the program represented by the following diagram clears CY with CLC 41 adds the content of LR 25 to a constant 6103 places the re sult in DM...

Page 167: ...Au Ad 1 Ad R 1 R CY CY ER Au and or Ad is not BCD Indirectly addressed DM word is non existent Content of DM word is not BCD or the DM area boundary has been exceeded CY ON when there is a carry in t...

Page 168: ...om plement to the true result subtract the content of R from zero see example below Mi Su CY CY R ER Mi and or Su is not BCD Indirectly addressed DM word is non existent Content of DM word is not BCD...

Page 169: ...one cycle resetting HR 2100 and then turned back ON 00000 LD 00002 00001 OUT TR 0 00002 CLC 41 00003 SUB 31 010 DM 0100 HR 20 00004 AND 25504 00005 CLC 41 00006 SUB 31 0000 HR 20 HR 20 00007 LD TR 0...

Page 170: ...1 and places the result in R and R 1 If the result is negative CY is set and the 10 s complement of the actual result is placed in R To convert the 10 s complement to the true result subtract the con...

Page 171: ...2100 00011 OUT HR 2100 CLC 41 SUBL 55 HR 20 120 DM 0100 CLC 41 SUBL 55 DM 0000 DM 0100 DM 0100 TR 0 25504 HR 2100 00003 25504 HR 2100 First subtraction Second subtraction Turned ON to indicate negativ...

Page 172: ...0 0 0 8 3 9 0 0 Md IR 013 3 3 5 6 Mr DM 0005 0 0 2 5 X Address Instruction Operands 00000 LD 00000 00001 MUL 32 013 DM 00005 HR 07 ER Md and or Mr is not BCD Indirectly addressed DM word is non existe...

Page 173: ...BCD IR SR AR DM HR TC LR Ladder Symbol Dr Divisor word BCD IR SR AR DM HR TC LR Operand Data Areas DIV 33 Dd Dr R R First result word BCD IR AR DM HR LR R and R 1 must be in the same data area When t...

Page 174: ...word BCD IR SR AR DM HR TC LR Ladder Symbols Operand Data Areas R First result word IR AR DM HR LR DIVL 57 Dd Dr R DIVL 57 Dd Dr R When the execution condition is OFF DIVL 57 is not executed When the...

Page 175: ...he rightmost seven digits are used for the mantissa and the leftmost digit is used for the exponent as shown in the diagram below The mantissa is expressed as a value less than one i e to seven decima...

Page 176: ...0 0 1 0 0 0 0 0 0 0 0 MSB LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB The following example shows how to divide two whole four digit numbers i e numbers without fractions so that a floating po...

Page 177: ...0000 MOV 21 0000 HR 02 MOV 21 4000 HR 01 MOV 21 4000 HR 03 MOVD 83 DM 0000 0021 HR 01 MOVD 83 DM 0000 0300 HR 00 MOVD 83 DM 0001 0021 HR 03 MOVD 83 DM 0001 0300 HR 02 FDIV 79 HR 00 HR 02 DM 0002 HR 01...

Page 178: ...t the words to be used are cleared to all zeros and then the value whose square root is to be taken is moved to Sq 1 The result which has twice the number of digits required for the answer because the...

Page 179: ...DM 0100 DM 0101 MOV 21 0000 DM 0103 0000 60170000 7756 932 DM 0103 IR 011 0 0 0 0 0 0 0 0 0000 0000 25505 5600 4900 IR 011 0 0 7 8 Address Instruction Operands Address Instruction Operands 00000 LD 00...

Page 180: ...en the execution condition is OFF ADB 50 is not executed When the execution condition is ON ADB 50 adds the contents of Au Ad and CY and places the result in R CY will be set if the result is greater...

Page 181: ...00 DM 0300 ADB 50 LR 21 DM 0201 DM 0301 ADB 50 0000 0000 DM 0302 Address Instruction Operands 00000 LD 00000 00001 CLC 41 00002 ADB 50 LR 20 DM 0200 DM 0300 00003 ADB 50 LR 21 DM 0201 DM 0301 00004 AD...

Page 182: ...negative CY is set and the 2 s complement of the actual result is placed in R Mi Su CY CY R ER Indirectly addressed DM word is non existent Content of DM word is not BCD or the DM area boundary has be...

Page 183: ...00003 SBB 51 010 DM 0100 HR 10 00004 SBB 51 011 DM 0101 HR 11 00005 AND 25505 00006 CLC 41 00007 SBB 51 0000 HR 10 HR 10 00008 SBB 51 0000 HR 11 HR 11 00009 LD TR 0 00010 AND NOT 25504 00011 MOV 21 0...

Page 184: ...IR SR AR DM HR TC LR Mr Multiplier word binary IR SR AR DM HR TC LR Ladder Symbols Operand Data Areas R First result word IR AR DM HR LR MLB 52 Md Mr R MLB 52 Md Mr R When the execution condition is O...

Page 185: ...directly addressed DM word is non existent Content of DM word is not BCD or the DM area boundary has been exceeded EQ ON when the result is 0 5 19 Logic Instructions The logic instructions COM 29 ANDW...

Page 186: ...ondition is ON ANDW 34 logically AND s the contents of I1 and I2 bit by bit and places the result in R 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 15 00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0...

Page 187: ...I1 Input 1 IR SR AR DM HR TC LR I2 Input 2 IR SR AR DM HR TC LR Ladder Symbols Operand Data Areas R Result word IR AR DM HR LR XORW 36 I1 I2 R XORW 36 I1 I2 R When the execution condition is OFF XORW...

Page 188: ...ine and the subroutine instructions are executed The instructions within a subroutine are written in the same way as main program code When all the subroutine instructions have been exe cuted control...

Page 189: ...a subroutine number N that is programmed as a definer for SBN 92 This same subroutine num ber is used in any SBS 91 that calls the subroutine see next subsection No subroutine number is required with...

Page 190: ...e to shift program execution from one subroutine to another i e subroutines may be nested When the second subroutine has been completed i e RET 93 has been reached program execution returns to the ori...

Page 191: ...ine number A subroutine has called itself Subroutines have been nested to more than sixteen levels Caution SBS 91 will not be executed and the subroutine will not be called when ER is ON 5 20 4 INTERR...

Page 192: ...umber is associated with each bit ac cording to the following table Interrupt Input Unit Subroutine Interrupt Input Unit Subroutine Unit no Bit no Unit no Bit no 0 0 00 2 0 16 1 01 1 17 2 02 2 18 3 03...

Page 193: ...first interrupt is not set To set the time interval for the scheduled interrupt set CC to 000 and set D to any value between 00 01 and 99 99 seconds The decimal point is not in put The time interval c...

Page 194: ...utine i e immediately after the sub routine has finished execution control returns to the point in the main pro gram where it was suspended SBN 92 99 INT 89 000 004 0002 RET 93 INT 89 001 004 0002 253...

Page 195: ...cing Interrupt input 2 Interrupt 2 servicing If two or more interrupt inputs are turned ON simultaneously the subroutine with the lowest subroutine number takes precedence For example interrupts from...

Page 196: ...grammed outside a block pro gram None of the following instructions can be used within a block program OUT OUT NOT TIM CNT END 01 IL 02 ILC 03 JMP 04 JME 05 STEP 08 SNXT 09 SFT 10 KEEP 11 CNTR 12 DIFU...

Page 197: ...2 NOT with a bit operand If the IF condition is YES the instructions immediately following the IF 02 or IF 02 NOT will be executed A YES execution condition is produced by an ON bit or ON execution co...

Page 198: ...e nested up to a maximum of 253 levels Each IF 02 or IF 02 NOT will be effective through the next ELSE 03 and or IEND 04 IF 02 IF 02 IF 02 IEND IEND IEND Flags No flags are affected by this instructio...

Page 199: ...F 02 25504 00018 MOV 21 0001 DM 0011 00019 IF 02 25503 00020 SET 07 00300 00021 IEND 04 00022 IEND 04 00023 ELSE 03 00024 SET 07 00301 00025 IEND 04 00026 BEND 01 5 21 5 ONE CYCLE AND WAIT WAIT 05 WAI...

Page 200: ...tructions within block 00 will be executed except WAIT 05 BPRG 96 00 WAIT 05 00001 A B BEND 01 C 00000 Address Instruction Operands 00000 LD 00000 00001 BPRG 96 00 A 00100 WAIT 05 00001 B 00200 BEND 0...

Page 201: ...first time the block program is entered When the block timer instruction is reached execution of the block program will halt until SV has expired at which time the second part of the block pro gram w...

Page 202: ...e the block program is entered When CNTW 14 is reached the execution of the block program will stop until SV has been reached at which time the second part of the block program will be executed Once t...

Page 203: ...for EXIT 06 NOT with an operand bit LD possibly in combination with AND or OR must be used to create an ex ecution condition for EXIT 06 when used without an operand bit Example In the following exam...

Page 204: ...correct LOOP 09 LOOP 09 IF 02 IF 02 IF 02 IF 02 IEND 04 IEND 04 IEND 04 LEND 10 LEND 10 Loops cannot be nested within loops Incorrect LOOP 09 LOOP 09 LEND 10 LEND 10 Do not reverse the order of LOOP a...

Page 205: ...o the application examples later in this section A step is like a normal programming code except that certain instructions e g IL 02 ILC 03 JMP 04 JME 05 may not be included 5 22 1 STEP DEFINE and STE...

Page 206: ...reset to their SVs Counters shift registers and bits used in KEEP 11 maintain status Two simple steps are shown below SNXT 09 20200 STEP 08 20200 00000 Step controlled by 20200 SNXT 09 20201 STEP 08...

Page 207: ...g turns ON for one cycle when STEP 08 is executed and can be used to reset counters in steps as shown below if neces sary SNXT 09 01000 CP R CNT 01 0003 00000 00100 25407 STEP 08 01000 1 Cycle 25407 0...

Page 208: ...art and end SW 1 SW 2 SW 3 SW 4 Loading Part installation Inspection discharge The following diagram demonstrates the flow of processing and the switches that are used for execution control Process A...

Page 209: ...amming for process C 00002 SW2 00003 SW3 00004 SW4 Process A started Process A reset Process B started Process B reset Process C started Process C reset Address Instruction Operands Address Instructio...

Page 210: ...cess A Printer SW D The following diagram demonstrates the flow of processing and the switches that are used for execution control Here either process A or process B is used depending on the status of...

Page 211: ...started Process C reset 00001 SW A1 SNXT 09 HR 0000 00002 SW B2 00001 SW A1 Address Instruction Operands Address Instruction Operands 00000 LD 00001 00001 AND NOT 00002 00002 SNXT 09 HR 0000 00003 LD...

Page 212: ...ocess D SW3 SW4 SW 1 and SW2 both ON SW5 and SW6 both ON The program for this operation shown below starts with two SNXT 09 in structions that start processes A and C These instructions branch from th...

Page 213: ...Programming for process C 00002 SW3 00005 SW7 Process A started Process A reset Process B started Process E reset 00001 SW1 and SW2 SNXT 09 LR 0000 SNXT 09 LR 0002 Process C started 01101 SNXT 09 LR...

Page 214: ...ing user error codes and messages counting ON bits setting the watchdog timer and refreshing I O during program execution 5 23 1 FAILURE ALARM FAL 06 and SEVERE FAILURE ALARM FALS 07 N FAL number 00 t...

Page 215: ...Programming Console GPC or FIT The displayed message can be up to 16 characters long i e each ASCII character code requires eight bits two dig its Refer to Appendix F for the extended ASCII codes Japa...

Page 216: ...8 G H DM 0014 4 9 4 A I J DM 0015 4 B 4 C K L DM 0016 4 D 4 E M N DM 0017 4 F 5 0 O P 5 23 3 BIT COUNTER BCNT 67 N Number of words BCD IR AR DM HR TC LR SB Source beginning word IR SR AR DM HR TC LR O...

Page 217: ...less Flags ER There are no flags affected by this instruction 5 23 5 I O REFRESH IORF 97 St Starting word IR I O word only Ladder Symbol E End word IR I O word only Operand Data Areas IORF 97 St E IOR...

Page 218: ...m the program or from the Programming Device A positive or negative delay can also be set to alter the actual point from which tracing will begin Data can be recorded in any of three ways TRSM 45 can...

Page 219: ...ded as the trace memory negative delay or that more samples will be made before they are recorded positive delay The sampled data is written to trace memory jumping to the beginning of the memory area...

Page 220: ...is a File Memory Unit mounted File memory transfers are done in blocks of 128 words File Memory Units are available with a capacity of either 1000 or 2000 blocks The blocks are numbered from zero Exe...

Page 221: ...designated PC memory area beginning at D If the destination memory area is too small to accommodate all of the transfer data only the portion that fits will be transferred D DM 0010 Block 0 S 0005 Bl...

Page 222: ...The data is transferred in 128 word blocks If the last block of the source transfer area does not have a full 128 words the unused words of the File Memory block will be empty D 0005 LR 20 S LR 20 LR...

Page 223: ...ransferred Because the transfer is done in block units any other data between the END 01 instruction and the block boundary is also transferred 00201 FILP 44 0002 Block no 0002 END 01 File Memory User...

Page 224: ...1 exceeds the data area boundary Indirectly addressed DM word is non existent Content of DM word is not BCD or the DM area boundary has been exceeded EQ OFF while data is being written ON when writin...

Page 225: ...data beginning at word S to addresses specified by D in the designated node on the SYSMAC NET Link SYSMAC LINK System The control words beginning with C specify the number of words to be sent the dest...

Page 226: ...Bit 15 Set to 1 C 2 Destination node 0 to 62 in 2 digit hexadecimal i e 00hex to 3Ehex Set to 0 The node number of the PC executing the send cannot be set Examples This example is for a SYSMAC NET Lin...

Page 227: ...umber to 0 to receive data to a node on the same Subsystem i e network Refer to the SYSMAC NET Link System Manual for details Word Bits 00 to 07 Bits 08 to 15 C Number of words 0 to 1000 in 4 digit he...

Page 228: ...t complete until the sending node receives and ac knowledges a response from the destination node Note that the SEND 90 RECV 98 Enable Flag is not turned ON until the first END 01 after the transmissi...

Page 229: ...s is performed when END 01 is executed in C2000H Duplex CPUs and during servicing of peripheral devices and Link Units for all other CPUs To ensure successful SEND 90 RECV 98 operations your program m...

Page 230: ...control data words to specify the 10 words to be transmitted to node 3 in operating level 1 of network 00 NSB Turns ON to indicate transmission error Transmitted data moved into words beginning at DM...

Page 231: ...D 12800 00012 AND 25203 00013 OUT 00200 00014 LD 12800 00015 AND 25204 00016 DIFU 13 12801 00017 LD 00001 00018 AND 25204 00019 AND NOT 12800 00020 LD 12803 00021 KEEP 11 12802 00022 LD 12802 00023 AN...

Page 232: ...ng the PC in order to achieve the desired control action at the right time This section explains the cycle and shows how to calculate the cycle time and I O response times I O response times in Link S...

Page 233: ...that occur during the cycle and the elements that affect cycle time is however essential to effective pro gramming and PC operations The major factors in determining program timing are the cycle time...

Page 234: ...error flags and lights indicator Resets watchdog timer and program address counter Executes program End of program Resets watchdog timer Refreshes input bits according to input signals ERROR ALARM Inp...

Page 235: ...l device servicing Host Link Unit servicing PC Link Unit servicing I and II Program execution Input refreshing Approx 3 0 ms sync time 1 0 ms 0 8 ms 18 s per output word 1 ms per Master plus 20 s per...

Page 236: ...II YES NO To input refreshing Servicing returns to the next item following the last one to be processed Host Link Unit servicing Peripheral servicing Because Link Unit and peripheral device servicing...

Page 237: ...les To simplify the examples the instructions used in the programs have been assumed to be all either LD or OUT The average execution time for the instructions is thus 0 6 s Operating times are given...

Page 238: ...s instruction times 20 000 instructions it is necessary to com pute the number of times that peripheral device and Link Unit servicing would be repeated to arrive at the actual output refreshing and U...

Page 239: ...overseeing time is fixed at 3 0 ms plus 1 0 ms for synchronization of Duplex CPUs or 4 0 ms The input refresh time is 3 Units x 25 s per 16 point Input Unit or 0 08 ms The output refreshing and Unit s...

Page 240: ...cution times for all instructions that are avail able for the C1000H and C2000H The maximum and minimum execution times and the conditions which cause them are given where relevant When word is referr...

Page 241: ...2 4 DM for SV 16 11 R 28 IL 11 JMP 11 R 18 IL 7 JMP 7 NOP 00 0 4 0 4 END 01 8 5 IL 02 9 6 8 6 ILC 03 9 6 7 5 JMP 04 10 7 9 6 JME 05 10 7 9 6 FAL 06 16 17 11 12 7 8 5 6 FAL 06 00 11 12 7 8 7 8 5 6 FALS...

Page 242: ...a constant to a word 16 17 10 11 7 8 5 6 When transferring DM to DM 30 31 20 21 BIN 23 When converting a word to a word 21 23 14 15 7 8 5 6 When converting DM to DM 34 35 22 23 BCD 24 When converting...

Page 243: ...ng DM 28 30 19 20 STC 40 9 10 6 7 6 8 4 6 CLC 41 9 10 6 7 6 8 4 6 FILR 42 When reading 1 block 4 89 ms 3 26 ms 6 8 4 6 When reading 20 blocks 81 9 ms 54 5 ms FILW 43 When writing 1 block 7 21 ms 4 8 m...

Page 244: ...When setting a constant to 1 word 35 37 23 24 7 8 5 6 When setting DM ms to 4 096 words using DM 4 14 ms 2 76 ms ROOT 72 When taking root of word and placing in a word 99 100 66 67 7 8 5 6 When takin...

Page 245: ...ng DM to DM 51 52 34 35 MOVD 83 When transferring word to a word 27 28 18 19 7 8 5 6 When transferring DM to DM 47 49 31 32 SFTR 84 When shifting 1 word 42 44 28 29 7 8 5 6 When shifting 4 096 DM word...

Page 246: ...sired output signal and then the input refresh and overseeing operations would have to be repeated before the output re fresh operation refreshes the output bit The I O response time in this case is t...

Page 247: ...ON delay cycle time x 2 overseeing time output ON delay The data in the following table would produce the minimum and maximum cycle times shown calculated below Input ON delay 1 5 ms Cycle time 20 ms...

Page 248: ...Monitoring Operation and Modifying Data 252 7 2 1 Bit Word Monitor 252 7 2 2 Force Set Reset 255 7 2 3 Hexadecimal BCD Data Modification 257 7 2 4 Hex ASCII Display Change 258 7 2 5 Three word Monitor...

Page 249: ...tion by pressing CLR FUN and then MONTR If an error message is displayed MONTR can be pressed to access any other error messages that are stored by the system in memory If MONTR is pressed in PROGRAM...

Page 250: ...K OK MEMORY ERR NO END INST I O BUS ERR I O SET ERR I O UNIT OVER SYS FAIL FALS SYS FAIL FAL DPL ERR RMTE I O ERR I O VER ERR SCAN TIME OVER 00000ERR CHK OK 7 1 2 Entering Debug Mode Debug mode cannot...

Page 251: ...is operation is used to execute a program on an instruction by instruction basis while examining the execution status at each step After Debug mode is entered the address from which execution is to be...

Page 252: ...nt instruction or indicates that a block program is being executed This status can be changed set or reset by using PLAY SET or REC RESET as long as B see below is not also being displayed Execution s...

Page 253: ...ng If END 01 is encountered before the stop address execution will halt Also program execution can be aborted by pressing CLR Key Sequence Stop address To abort Address currently set Example Address c...

Page 254: ...be traced If the stop address or END 01 lies within the trace area trace execution will go only as far as the stop address or the END 01 and then will loop back over the instructions at the start of...

Page 255: ...P ADRS 02121 00000RUN TRIG ADRS 00000 00000RUN TRIG ADRS 01000 00000RUN DELAY 000 00000RUN DELAY 211 RUN G 00000 DEBUG 00000 STEP 0 LD 00000 00000RUN STOP ADRS 00000 00000 STEP 0 LD 00000 00800 RUN HA...

Page 256: ...1 LD 00000 00999 001 0 OUT 00102 00998 002 1 AND 00003 Meaning of Displays 0 OFF 1 ON B Block program execution IL Within an IL ILC block JP Within a JMP JME block NP Block program not executed Addre...

Page 257: ...the digit contents of the word will be displayed and when a timer or counter number is designated the PV of the timer will be displayed and a small box will appear if the completion flag of a timer or...

Page 258: ...y Sequence Cancels monitor operation Clears leftmost address The following examples show various applications of this monitor operation Program Read then Monitor Indicates Completion flag is ON Monito...

Page 259: ...254 Bit Monitor 00000 00000 LD 00001 00001 ON 00000 CONT 00001 Word Monitor 00000 00000 CHANNEL 000 00000 CHANNEL LR 01 cL01 FFFF cL00 0000 Monitoring Operation and Modifying Data Section 7 2...

Page 260: ...be pressed to turn ON the bit start the timer or increment the counter and REC RESET can be pressed to turn OFF the bit or reset the timer or counter Timers will not oper ate in PROGRAM mode SR bits c...

Page 261: ...low ing program section 00002 TIM 000 00500 012 3 s Address Instruction Operands 00200 LD 00002 00201 TIM 000 0123 00202 LD TIM 000 00203 OUT 00500 TIM 000 0123 The following displays show what happen...

Page 262: ...OFF ON T0000010000500 0123 OFF OFF T0000010000500 0000 ON ON T0000010000500 0123 ON OFF T0000010000500 0122 ON OFF T0000010000500 0000 ON ON 0010000500 OFF OFF 0010000500 ON OFF 7 2 3 Hexadecimal BCD...

Page 263: ...ode Timing Timing PV changed Timing Timing 00000 00000 TIM 000 T000 0122 00000PRES VAL T000 0119 00000PRES VAL T000 0100 0200 T000 0199 7 2 4 Hex ASCII Display Change This operation converts DM data d...

Page 264: ...ecify the lowest numbered word press MONTR and then press EXT to display the data contents of the specified word and the two words that follow it A CLR entry changes the three word monitor operation t...

Page 265: ...s the contents of a word during the 3 word Monitor op eration The blinking square indicates where the data can be changed After the new data value is keyed in pressing WRITE causes the original data t...

Page 266: ...2345 89AB D0002D0001D0000 0001 4567 89AB 7 2 7 Binary Monitor You can specify that the contents of a monitored word be displayed in binary by pressing SHIFT and MONTR after the word address has been i...

Page 267: ...IR HR AR LR or DM word The cursor which can be shifted to the left with the up key and to the right with the down key indicates the position of the bit that can be changed After positioning to the de...

Page 268: ...nd decrementing the SV is possible only when the SV has been entered as a constant To use either method first display the address of the timer or counter whose SV is to be changed presses the down key...

Page 269: ...nd incrementing to a new constant 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DATA 0123 00201 TIM DATA T000 0123 00201 TIM DATA T000 0123 0124 00201 TIM DATA 0124 00201 DATA T000 0123 c 00201 DATA...

Page 270: ...0 00000 TIM 000 00201SRCH TIM 000 00201 TIM DATA 0123 00201 TIM DATA T000 0123 00201DATA U D T000 0123 0123 00201DATA T000 0123 0122 00201DATA T000 0123 0123 00201DATA T000 0123 0124 00201DATA T000 01...

Page 271: ...PROGRAM modes The Programming Console operations described in this section can be can celled by pressing CLR during or after the normal key sequence 7 3 1 File Memory Clear This operation clears the...

Page 272: ...ransferred to the FM area with this operation Data is written in blocks of 128 words When transferring from program memory data between the specified starting address and the next END 01 in the progra...

Page 273: ...transfer from the DM area you must specify the number of blocks to be transferred Key Sequence Start block Start address Start DM Wd No of blocks Start block Start Wd AR File Memory Operations Section...

Page 274: ...30FM MEM UM 00130FM MEM UM START BLOCK 00130FM MEM UM START BLOCK 0010 00130FM MEM UM XFER G 00130FM MEM UM XFER END 0051 00000FM MEMIOM D 00000FM MEMIOM D1234 00000FM MEMIOM BLOCK NO 00000FM MEMIOM B...

Page 275: ...ng Console When data in program memory is being verified this operation compares program memory data starting at the specified address and ranging to END 01 to FM data starting at a specified block th...

Page 276: ...M 00130FM MEMUM 00130FM MEMUM START BLOCK 00130FM MEMUM START BLOCK 0010 00130FM MEMUM VER G 00130FM MEMUM VER END 0051 00000FM MEMIOM D 00000FM MEMIOM D1234 00000FM MEMIOM BLOCK NO 00000FM MEMIOM BLO...

Page 277: ...red in blocks of 128 words When reading data to be transferred to program memory reading begins at the specified FM start block Reading and block transfer end when either the first END 01 or non UM i...

Page 278: ...273 Key Sequence Start block Start address Start DM Wd No of blocks Start block Start Wd AR File Memory Operations Section 7 3...

Page 279: ...30FM MEM UM 00130FM MEM UM START BLOCK 00130FM MEM UM START BLOCK 0010 00130FM MEM UM XFER G 00130FM MEM UM XFER END 0051 00000FM MEMIOM D 00000FM MEMIOM D1234 00000FM MEMIOM BLOCK NO 00000FM MEMIOM B...

Page 280: ...If you do not specify a start block the reading will begin at the first block of the FM area To access words within the current block use the up and down keys to scroll through word by word or to go...

Page 281: ...MREAD DISABLED CM 7 4 Program Backup and Restore Operations Both Program Memory UM and DM area data can be backed up on a stan dard commercially available cassette tape recorder Any dependable mag net...

Page 282: ...pe and or the PC MT ERR Cassette tape is faulty Replace it with another 7 4 1 Saving Program Memory Data This operation is used to copy the content of Program Memory to a cassette tape The procedure i...

Page 283: ...DDR 03890 00345MT STOP ADDR 05789 00345MT RECORD FILE NO 86031400 02420MT RECORD FILE NO 86031400 04801MT RECORD END 01 05 6KW 04801MT DISCONTD END 01 05 6KW 05789RECORD END END 01 06 8KW 7 4 2 Restor...

Page 284: ...ich time the program size in Kwords is dis played At that time the program size in Kwords is displayed Even if END 01 is reached before the end of the tape the restoring or comparison operation will c...

Page 285: ...8KW 16789VER OK END 01 16 8KW 00000MT FILE NO 86031400 00000MT START ADDR 00000 00000MT START ADDR 12345 7 4 3 Saving Restoring and Comparing DM Data The procedures for saving restoring and comparing...

Page 286: ...ds Recording in progress Recording stopped using CLR key Recording stops at the end 00000 00000MT UM 0 DM 1 D0000MT FILE NO 00000000 D0000MT FILE NO 00000012 D0000MT RECORD FILE NO 00000012 D0127MT RE...

Page 287: ...Key Verification stopped at the end 00000 00000MT UM 0 DM 1 D0000MT FILE NO 00000000 D0000MT FILE NO 00000012 D0000MT VER FILE NO 00000012 D0127MT VER FILE NO 00000012 D0127MT DISCONTD FILE NO 000000...

Page 288: ...ey Restoring stopped at the end 00000 00000MT UM 0 DM 1 D0000MT FILE NO 00000000 D0000MT FILE NO 00000012 D0000MT PLAY FILE NO 00000012 D0127MT PLAY FILE NO 00000012 D0127MT DISCONTD FILE NO 00000012...

Page 289: ...Key Verification stopped at the end 00000 00000MT UM 0 DM 1 D0000MT FILE NO 00000000 D0000MT FILE NO 00000012 D0000MT VER FILE NO 00000012 D0127MT VER FILE NO 00000012 D0127MT DISCONTD FILE NO 000000...

Page 290: ...tware errors that occur during PC operation Program input and program syntax errors are described in Section 4 Writing and Inputting the Program Although described in Section 3 Memory Areas flags and...

Page 291: ...a FAL number which is output to the same loca tion in the SR area when FALS 07 is executed Executing FALS 07 will stop PC operation and will cause all outputs from the PC to be turned OFF When FAL 06...

Page 292: ...er supply to Remote I O Units connections between Remote I O Units and terminator setting The following error messages appear for errors that occur after program exe cution has been started PC operati...

Page 293: ...ply Unit CPU error No message None Watchdog timer has exceeded maximum setting default setting 130 ms Restart system in PROGRAM mode and check program Reduce cycle time or reset watchdog timer if long...

Page 294: ...ailed within this manual Errors in program input and debugging can be examined in Sections 4 6 2 and 4 6 3 and errors in cassette tape operation are detailed in Section 7 4 8 5 Error Flags The followi...

Page 295: ...Fuse blows repeatedly Voltage selector terminal setting error Connect the voltage selector terminal correctly Circuit board is short circuited or burnt Replace CPU Rack Power Supply Unit or Backplane...

Page 296: ...is defective Replace defective Input Unit Input bit is incorrectly programmed in OUTPUT instruction Correct the program One input point does not turn OFF Input circuit is defective Replace defective...

Page 297: ...tput circuit is defective Replace defective Unit One output does not turn OFF but i di t d t li ht Output relay is defective Replace defective relay p indicator does not light Leakage current or resid...

Page 298: ...voltage 12 5 V ROM ID B Duplex Unit For C2000H duplex system 3G2C5 DPL01 E CPU Power Supply 100 to 120 200 to Output 7 A 5 VDC 3G2A5 PS221 E 240 VAC selectable Output 12 A 5 VDC 3G2A5 PS223 E 24 VDC...

Page 299: ...VDC Output 7 A 5 VDC 3G2A5 PS212 E I O Interface Unit 3G2A5 II002 I O Connecting Cable Vertical type 30 cm C500 CN312N 50 cm C500 CN512N 80 cm C500 CN812N 1 m C500 CN122N 2 m C500 CN222N For I O Unit...

Page 300: ...DC 8 points common 2 circuits 16 pts 3G2A5 OC221 p Unit 2 A 250 VAC 24 VDC sep commons 16 pts 3G2A5 OC223 2 A 250 VAC 24 VDC 8 points common 4 circuits 32 pts 3G2A5 OC224 E Transistor 1 A 12 to 24 VDC...

Page 301: ...3G2A5 CT001 6 BCD digits 50 K cps 8 Set Value 1 pt 3G2A5 CT012 4 BIN digits 20 K cps 1 Set Value 4 pt C500 CT041 Magnetic Card Reader 3G2A5 MGC01 Connecting Cable 3G2A9 CN521 Card Reader 3S4YR MAW2C 0...

Page 302: ...MAC Net General purpose C500 SNT31 V4 SYSMAC Link Use optical fiber cable C1000H SLK11 Only for C1000H and C2000H Simplex C1000H SLK21 V1 Optical Remote I O Master APF PCF 3G2A5 RM001 PEV1 PCF 3G2A5 R...

Page 303: ...G2A9 AL001 Optical APF PCF 3pcs 3G2A9 AL002 PE Optical PCF 3pcs 3G2A9 AL002 E Optical APF PCF RS 422 RS 232C 1 pc each 3G2A9 AL004 PE Optical PCF RS 422 RS 232C 1 pc each 3G2A9 AL004 E Optical APF PCF...

Page 304: ...diagram illustrates the model number for cables with connectors tension members and power lines are provided in the cable Half lock connectors use the S3200 COCF2511 and are compatible with C200H SYS...

Page 305: ...F62M SYSMAC NET Relay F Connector S3200 COCF62F Cable Assembly Tool and Cutter Name Model Cable Assembly Tool S3200 CAK1062 Optical Power Tester Name Model SYSMAC NET CV500 SNT31 S3200 CAT2000 SYSMAC...

Page 306: ...0 AP003 Connecting Cable 2 m C200H CN222 4 m C200H CN422 PROM Writer Write voltage 12 5 21 V applicable 3G2A5 PRW06 Printer Interface Unit Memory Pack is separate 3G2A5 PRT01 E Memory Pack for Printer...

Page 307: ...ecial type 3G2A5 COV11 For 38 pin block standard C500 COV12 For 20 pin block standard C500 COV13 Connector Cover For I O connector 3G2A5 COV01 For Link connector 3G2A5 COV02 For I O Control Unit I O I...

Page 308: ...NOT LD NOT 45 108 OR OR 46 108 OR NOT OR NOT 46 108 OR LOAD OR LD 50 109 OUTPUT OUT 48 109 OUTPUT NOT OUT NOT 48 109 TIMER TIM 118 00 NO OPERATION NOP 116 01 END END 48 107 116 02 INTERLOCK IL 88 113...

Page 309: ...NARY ADD ADB 174 51 BINARY SUBTRACT SBB 176 52 BINARY MULTIPLY MLB 178 53 BINARY DIVIDE DVB 179 54 DOUBLE BCD ADD ADDL 161 55 DOUBLE BCD SUBTRACT SUBL 164 56 DOUBLE BCD MULTIPLY MULL 166 57 DOUBLE BCD...

Page 310: ...ETURN RET 183 94 WATCHDOG TIMER REFRESH WDT 211 96 BLOCK PROGRAM BEGIN BPRG 190 97 I O REFRESH IORF 211 98 NETWORK RECEIVE RECV 221 01 BLOCK PROGRAM END BEND 190 02 CONDITIONAL BRANCH IF 191 03 NO BRA...

Page 311: ...4 0 4 OR NOT 0 4 0 4 0 4 0 4 AND LD 0 4 0 4 0 4 0 4 OR LD 0 4 0 4 0 4 0 4 OUT 0 8 0 8 0 8 0 8 OUT NOT 0 8 0 8 0 8 0 8 TIM 2 4 2 4 Constant for SV R 2 4 IL 2 4 JMP 2 4 20 13 DM for SV R 29 IL 29 JMP 14...

Page 312: ...word 7 8 5 6 5 59 ms 3 72 ms When shifting 4 096 words using DM CMP 20 14 9 When comparing a constant to a word 7 5 29 20 When comparing two DM MOV 21 15 17 10 11 When transferring a constant to a wor...

Page 313: ...DM DM XORW 36 19 21 13 14 Constant XOR word word 7 8 5 6 40 41 27 28 DM XOR DM DM XNRW 37 20 21 13 14 Constant XNOR word word 7 8 5 6 40 41 27 28 DM XNOR DM DM INC 38 23 25 15 16 When incrementing a w...

Page 314: ...ord 7 8 5 6 Bit Count 8 2 ms 5 5 ms When counting 4 096 words using DM BCMP 68 66 68 44 45 Comparing constant to word designated table 7 8 5 6 95 96 63 64 Comparing DM DM designated table XFER 70 46 4...

Page 315: ...8 5 6 47 49 31 32 DM DM DM COLL 81 28 30 19 20 Word word word 7 8 5 6 48 50 32 33 DM DM DM MOVB 82 31 32 21 22 When transferring word to a word 7 8 5 6 51 52 34 35 When transferring DM to DM MOVD 83...

Page 316: ...specifying the data area as DM and then entering the address of the DM word that contains the actual data Basic Instructions Name and Mnemonic Symbol Function Operand Data Areas Page AND AND B Logical...

Page 317: ...n B IR SR HR AR LR TC 108 OR LOAD OR LD Logically ORs the resultant execution conditions of the preceding logic blocks None 109 OR NOT OR NOT B Logically ORs the inverse of the designated bit with the...

Page 318: ...corresponding JMP 04 and JME 05 instructions have the same N value in the range 01 through 99 Direct jumps are usable only once each per program i e N is 01 through 99 can be used only once each and...

Page 319: ...SV CNTR 12 Increases or decreases the PV by one whenever the increment input II or decrement input DI signals respectively go from OFF to ON SV 0 to 9999 R reset input Each TC bit can be used for one...

Page 320: ...R LR DM 136 BCD TO BINARY BIN 23 BIN 23 S R Converts 4 digit BCD data in source word S into 16 bit binary data and outputs converted data to result word R S x100 x101 x102 x103 x160 x161 x162 x163 BCD...

Page 321: ...0 moving to carry CY and CY moving to bit 15 Wd IR HR AR LR DM 133 COMPLEMENT COM 29 COM 29 Wd Inverts bit status of one word Wd of data changing 0s to 1s and vice versa Wd Wd Wd IR HR AR LR DM 179 BC...

Page 322: ...bits in the input words are both ON I1 I2 IR SR HR AR LR TC DM R IR HR AR LR DM 180 OR WORD ORW 35 ORW 35 I1 I2 R Logically ORs two 16 bit input words I1 and I2 and sets the bits in the result word R...

Page 323: ...r of blocks to be transferred S specifies the starting source block D specifies the address of the starting destination word PC memory S S N 1 D File memory N S IR SR HR AR LR TC DM D IR HR AR LR TC D...

Page 324: ...amples which are written to the Trace Memory of the GPC FIT or LSS A positive or negative delay can be set for the recording of the samples AR 1813 and 1812 indicate tracing in progress and tracing co...

Page 325: ...HR AR LR DM 178 BINARY DIVIDE DVB 53 DVB 53 Dd Dr R Divides the 4 digit hexadecimal dividend Dd by the 4 digit divisor Dr and outputs result to the designated result words R and R 1 R and R 1 must be...

Page 326: ...57 DIVL 57 Dd Dr R Divides the 8 digit BCD dividend by an 8 digit BCD divisor and outputs the result to the specified result words All words for any one operand must be in the same data area Dd 1 Dd...

Page 327: ...comparison block If the value falls within any of the ranges the corresponding bits in the result word R will be set The comparison block must be within one data area S CB CB 1 CB 2 CB 3 CB 4 CB 5 CB...

Page 328: ...fied result word R Sq and Sq 1 must be in the same data area Sq 1 Sq R Sq IR SR HR AR LR TC DM R IR HR AR LR DM 172 DATA EXCHANGE XCHG 73 XCHG 73 E1 E2 Exchanges the contents of two words E1 and E2 E1...

Page 329: ...4 ENCODER DMPX 77 DMPX 77 S R Di Determines the position of the leftmost ON bit in the source word s starting word S and turns ON the corresponding bit s in the specified digit of the result word R On...

Page 330: ...IR SR HR AR LR TC DM R IR HR AR LR DM 169 SINGLE WORD DISTRIBUTE DIST 80 DIST 80 S DBs Of Moves one word of source data S to the destination word whose address is given by the destination base word D...

Page 331: ...git gives the first source digit The next digit to the left gives the number of digits to be moved The next digit specifies the first digit in the destination word S D 15 00 S IR SR HR AR LR TC DM Di...

Page 332: ...LR TC DM TB R IR HR AR LR TC DM 146 ASCII CONVERT ASC 86 ASC 86 S Di D Converts hexadecimal digits from the source word S into 8 bit ASCII values starting at leftmost or rightmost half of the startin...

Page 333: ...duled interrupt In IIUs bits 00 to 07 identify the interrupting subroutine higher bits are not used Bit 00 of Unit 0 corresponds to interrupt subroutine 00 through to bit 07 of Unit 3 which correspond...

Page 334: ...stination node number is set to 0 data is transmitted to all nodes For SYSMAC LINK Systems the right half of C 1 specifies the response monitoring time default 00 2 s FF monitoring disabled the next d...

Page 335: ...T Sets the maximum and minimum limits for the watchdog timer normally 0 to 130 ms New limits Maximum time 130 100 x T Minimum time 130 100 x T 1 T 0 to 63 211 BLOCK PROGRAM START BPRG 96 BPRG 96 N In...

Page 336: ...the type of system In both types of systems the first control word C gives the number of words to be transferred For NET Link Systems in the second word C 1 bit 14 specifies the system 0 for system 1...

Page 337: ...ogram portion that has started with IF 02 None 191 ONE CYCLE AND WAIT WAIT 05 WAIT 05 B WAIT 05 NOT B WAIT 05 WAIT 05 NOT Halts execution of a block program until a specified condition is satisfied B...

Page 338: ...N 0 to 99 198 TIMER WAIT TIMW 13 N SV TIMW 13 The execution of the block program between the TIMW 13 instruction and BEND 04 is not executed until the set value of the specified timer has been reache...

Page 339: ...m Search Searches a program for the specified data address or instruction 82 Instruction Insert Instruction Delete Allows a new instruction to be inserted before the displayed instruction or deletes t...

Page 340: ...ogram Memory Compare Compares Program Memory data on tape with that in the Program Memory area 278 DM Data Save Restore Compare Save restore and compare tape operations for DM area data 280 File Memor...

Page 341: ...when performing a partial memory clear with each of the memory areas entered being retained Specifying an address will result in the Program Memory after and including that address being deleted All...

Page 342: ...ot be specified R P M CLR FUN SHIFT CH MONTR Rack no Unit no MONTR SHIFT SHIFT I O Table Transfer Transfers a copy of the I O Table to RAM so that the table and and the user program can be written to...

Page 343: ...nd press WRITE after each P Address displayed Instruction word Operand Program Read Allows the user to scroll through the program address by address If the Program Memory is read in RUN or MONITOR mod...

Page 344: ...that there are no empty addresses or instructions without addresses P INS At the desired position in program DEL Instruction currently displayed Enter new instruction Insert Delete Program Check Once...

Page 345: ...pressed P EXT CHG CLR Stop address To cancel Debug operation Address Trace Traces up to 250 instructions from the program Tracing begins at the address indicated by the trigger address and the delay...

Page 346: ...o words that follow Pressing CLR will change the three word monitor operation into a single word display R P M EXT Bit Word monitor in progress Currently monitored words ap pear on the left of the scr...

Page 347: ...WRITE New SV WRITE All EXT 3 word Change This operation changes the value of a word displayed during a 3 word Monitor operation The blinking cursor indicates the word that will be affected by the oper...

Page 348: ...r The contents of a monitored word can be specified to be displayed in binary by pressing SHIFT and MONTR after entering the word address Words can be scrolled by pressing the up and down keys to incr...

Page 349: ...ad operation will proceed from the specified start address up to the end of the tape unless halted by a CLR command The instruction must be completed before the required data is reached on the tape i...

Page 350: ...s and then pressing the down key To change the content of the displayed word enter the new data and press WRITE Program and comment data stored in the FM area cannot be modified using this operation P...

Page 351: ...TIM CNT AR Program Memory Other data areas DM area File Memory Verify Compares the data stored in the FM area with data in the Program Memory or specified data areas When comparing with data in the P...

Page 352: ...instructions TIM TIMW 13 CNT CNT 14 TMHW 15 and CNTR 12 are ex ecuted when ER is ON other instructions with a vertical arrow under the ER column are not executed if ER is ON All of the other flags in...

Page 353: ...END 01 OFF OFF OFF OFF OFF STEP 08 SNXT 09 CNTR 12 TIMH 15 WSFT 16 CMP 20 MOV 21 MVN 22 BIN 23 BCD 24 ASL 25 ASR 26 ROL 27 ROR 28 COM 29 ADD 30 SUB 31 MUL 32 DIV 33 ANDW 34 ORW 35 XORW 36 XNRW 37 INC...

Page 354: ...P 44 TRSM 45 MSG 46 ADB 50 SBB 51 MLB 52 DVB 53 ADDL 54 SUBL 55 MULL 56 DIVL 57 BINL 58 BCDL 59 FUN67 BCMP 68 XFER 70 BSET 71 ROOT 72 XCHG 73 SLD 74 SRD 75 MLPX 76 DMPX 77 SDEC 78 FDIV 79 DIST 80 COLL...

Page 355: ...R 25506 EQ 25507 LE WRIT 87 READ 88 FUN89 SEND 90 SBS 91 SBN 92 RET 93 WDT 94 BPRG 96 IORF 97 RECV 98 BEND 01 IF 02 ELSE 03 IEND 04 WAIT 05 EXIT 06 SET 07 RSET 08 LOOP 09 LEND 10 BPPS 11 BPRS 12 TIMW...

Page 356: ...g this table HR HR 0000 to HR 9915 HR 00 to HR 99 HR bits are available for general data storage and manipulation The HR area maintains data when PC power is turned off AR AR 0000 to AR 2715 AR 00 to...

Page 357: ...el 1 of SYSMAC LINK or SYSMAC NET Link System 246 00 to 15 Not used 247 to 250 00 to 07 PC Link Unit Run Flags or data link status for operating level 1 08 to 15 PC Link Unit Run Flags or data link st...

Page 358: ...C LINK System 08 to 15 Not used May be used as work bits 08 to 10 00 to 15 Active Node Flags for SYSMAC LINK System nodes of 11 00 to 13 operating level 0 11 14 Communications Controller Error Flag fo...

Page 359: ...to 15 FM Blocks Counter 21 00 to 15 Remaining FM Blocks Counter 22 00 to 11 On line Removal First Word Indicator 12 to 14 Number of Words Indicator for On line Removal 15 On line Removal Flag 23 00 to...

Page 360: ...ment Records Sheets This appendix contains sheets that can be copied by the programmer to record I O bit allocations and terminal assignments on the Racks as well as details of work bits data storage...

Page 361: ...tes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word Unit Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word Unit Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 1...

Page 362: ...age Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area Word Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area Word Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13...

Page 363: ...I O Assignment Records Sheets Appendix F 360 Programmer Program Date Page Word Contents Notes Word Contents Notes Data Storage...

Page 364: ...Appendix F I O Assignment Records Sheets 361 Programmer Program Date Page TC address T or C Set value Notes TC address T or C Set value Notes Timers and Counters...

Page 365: ...designed for flexibility al lowing the user to input all required addresses and instructions When coding programs be sure to specify all function codes for instructions and data areas or for constant...

Page 366: ...Program Coding Sheet Appendix G 364 Programmer Program Date Page Address Instruction Operand s Address Instruction Operand s...

Page 367: ...Appendix G Program Coding Sheet 365 Programmer Program Date Page Address Instruction Operand s Address Instruction Operand s...

Page 368: ...00010001 0B 00001011 12 00010010 0C 00001100 13 00010011 0D 00001101 14 00010100 0E 00001110 15 00010101 0F 00001111 16 00010110 10 00010000 17 00010111 11 00010001 18 00011000 12 00010010 19 0001100...

Page 369: ...q 1 A Q a q 0010 2 STX DC2 2 B R b r 2 B R b r 0011 3 ETX DC3 3 C S c s 3 C S c s 0100 4 EOT DC4 4 D T d t 4 D T d t 0101 5 ENQ NAK 5 E U e u 5 E U e u 0110 6 ACK SYN 6 F V f v 6 F V f v 0111 7 BEL ET...

Page 370: ...al I O Unit used to program in BASIC When connected to an NSU on a SYSMAC NET Link System commands can be sent to other nodes Backplane A base onto which Units are mounted to form a Rack Backplanes pr...

Page 371: ...e but not all of the lad der diagram instructions buffer A temporary storage space for data in a computerized device building block PC A PC that is constructed from individual components or building b...

Page 372: ...it and used to count the number of times the status of a bit or an execution condition has changed from OFF to ON CPU An acronym for central processing unit In a PC System the CPU executes the program...

Page 373: ...n is called the source differentiated instruction An instruction that is executed only once each time its execution condition goes from OFF to ON Nondifferentiated instructions are executed each cycle...

Page 374: ...nd up to the instruction currently being executed execution time The time required for the CPU to execute either an individual instruction or an entire program Expansion I O Backplane A Backplane whic...

Page 375: ...ating in the hardware structure electronic components of the PC as opposed to a software error which originates in software i e pro grams hexadecimal A number system where all numbers are expressed to...

Page 376: ...lated group of instructions could be called an instruc tion block the term is generally used to refer to blocks of instructions called logic blocks that require logic block instructions to relate them...

Page 377: ...an input signal received from an external device I O table A table created within the memory of the PC that lists the IR area words allo cated to each Unit in the PC System The I O table can be create...

Page 378: ...o which Link Units can be mounted Link System A system that includes one or more of the following systems Remote I O System PC Link System Host Link System or SYSMAC NET Link System Link Unit Any of t...

Page 379: ...eftmost bit word NC input An input that is normally closed i e the input signal is considered to be present when the circuit connected to the input opens nest Programming one loop within another loop...

Page 380: ...is said to be present The ON state is generally represented by a high voltage or by conductivity but can be defined as the opposite of either ON delay The delay between the time when an ON signal is...

Page 381: ...tment of the number of ON bits in a word or other unit of data so that the total is always an even number or always an odd number Parity is gener ally used to check the accuracy of data after being tr...

Page 382: ...esigned to gener ate the alarm in the program as opposed to one generated by the system programmed error An error arising as a result of the execution of an instruction designed to gen erate the error...

Page 383: ...t The process of turning a bit or signal OFF or of changing the present value of a timer or counter to its set value or to zero return The process by which instruction execution shifts from a subrouti...

Page 384: ...at uses a Simplex CPU Slave Short for Remote I O Slave Unit Slave Rack A Rack containing a Remote I O Slave Unit and controlled through a Remote I O Master Unit Slave Racks are generally located away...

Page 385: ...e An error message generated by the system as opposed to one resulting from execution of an instruction designed to generate a message TC area A data area that can be used only for timers and counters...

Page 386: ...m that ensures that the cycle time stays within speci fied limits When limits are reached either warnings are given or PC opera tion is stopped depending on the particular limit that is reached Wired...

Page 387: ...g Program Memory data 278 280 constants operands 103 control bit Data Retention 28 data tracing 34 definition 16 File Memory 34 manipulating 23 Output OFF 29 Control System definition 3 controlled sys...

Page 388: ...286 resetting 209 SR and AR area flags 289 troubleshooting 290 execution condition definition 44 execution time instructions 235 240 program 230 Expansion I O Rack definition 12 F Factory Intelligent...

Page 389: ...34 180 ASC 86 157 ASL 25 131 ASR 26 132 BCD 24 149 BCDL 59 150 BCMP 68 145 BCNT 67 210 BEND 01 190 BIN 23 148 BINL 58 148 BPPS 11 198 BPRG 96 190 BPRS 12 198 BSET 71 136 CLC 41 159 CMP 20 142 CNT 122...

Page 390: ...88 IR area 18 23 J jump numbers 115 jumps 115 116 L ladder diagram branching 86 IL 02 and ILC 03 88 using TR bits 86 controlling bit status using DIFU 13 and DIFD 14 92 110 111 using KEEP 11 112 117 u...

Page 391: ...s program execution 97 Program Memory 39 backup and restore 278 280 setting address and reading content 75 76 structure 44 programming backup onto cassette tape 276 284 checks for syntax 79 81 display...

Page 392: ...in TC area 37 block programs 195 changing SV 263 conditions when reset 118 122 example using CMP 20 143 extended 119 flicker bits 120 inputting SV 76 ON OFF delays 119 one shot bits 120 TR area 39 TR...

Page 393: ...tail and in cludes standardized terms Scan time has been replaced by cycle time throughout the manual Page 7 Catalogue number for the SYSMAC LINK System Manual was cor rected Page 20 Model number CT04...

Page 394: ...adquarters OMRON EUROPE B V Wegalaan 67 69 NL 2132 JD Hoofddorp The Netherlands Tel 31 2356 81 300 Fax 31 2356 81 388 OMRON ELECTRONICS LLC 1 East Commerce Drive Schaumburg IL 60173 U S A Tel 1 847 84...

Page 395: ...Cat No W140 E1 04 Note Specifications subject to change without notice Printed in Japan Authorized Distributor...

Page 396: ...Cat No W140 E1 04 SYSMAC C1000H C2000H Programmable Controllers OPERATION MANUAL...

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