Omron 3G8F7-CRM21, User Manual

Page: 80 / 238

60
Communications Cycle Control Procedures
Section 5-2
5-2-2 Controls from the Initial Process to Communications Cycle
Startup
Step Operation procedure Access to Shared Memory
1. Confirm the PCI
resources. Get the base address of shared memory space and the
Interrupt line from the Board ID and the contents in the
PCI configuration register.
2. Set the interrupt mask.
Write 0x0000 in the Interrupt Mask (0x0004) of "Board
→
PC Interrupt", to prevent any interrupts.
3. Confirm the INIEND (or
Notification of Initial
process ends)
Poll the Interrupt Cause (0x0005) in "Board
→
PC
Interrupt", and wait until INIEND is 1. After it is confirmed,
write 1 in INIEND of the Interrupt Clear register (0x0006)
to clear the interrupt cause.
4. Confirm the initializing
ends. Confirm 0x1703 is stored in the Initialization end
notification (0x0010) of the shared memory.
If 0x0905 (RAM error) is stored, there may be a hardware
error.
5. Confirm the operation
mode. Check the Running program ID (0x0012) in the shared
memory, and confirm the 0xFFFF (OPEN_SYSTEM
command wait state) is stored.
If any other value is stored, reset the Board by the Board
reset (0x0001), and redo from the Step 1.
6. Set the software table
and the data rate. Set the Software Table (0x3900) and the Data Rate
(0x3908) in the setting area group.
7. Make the detailed
settings when the
OPEN_SYSTEMEX is
used. When the OPEN_SYSTEMEX is used, set the Logic Error
Check Item (0x390A), the Registration Table (0x390C),
the Network Parameter (0x4692) and/or the Slave Unit
Parameter (0x469C), if any of them is required.
8. Set the initial value for
OUT data if necessary. To set the initial values in the OUT data, write them in the
OUT Data (0x0200) and the Bit OUT Data (0x0280).
When no initial values are set, 0 is assigned as the initial
value.
9. Set the commands for
OPEN_SYSTEM or
OPEN_SYSTEMEX. Set the command OPEN_SYSTEM or
OPEN_SYSTEMEX in the Command area (PC
→
BD)
(0x3200).
10. Notify the command is
set. Set the CMD flag of the Interrupt Trigger register (0x0002)
to 1.
11. Confirm the command
set has been notified. Confirm the CMD flag of the Interrupt Request
Confirmation register (0x0003) changes to 0.
12. Wait for a command
acknowledgment. Confirm the CMD_ACK flag of the Interrupt Cause
register (0x0005) changes to 1. (Check it by an interrupt
or polling.)
13. Read a command
response. Read a command response from the CompoNet Master
board, which is stored in the Command area (BD
→
PC)
(0x3210).
14. Release a command
acknowledgment
interrupt. Release the Interrupt cause by setting the CMD_ACK flag
of the Interrupt Clear register (0x0006).