OKIDATA DOC-IT3000, Service Manual

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Service Guide DOC-IT3000/4000
Chapter 2 Principles of Operation
2.3.03 Doc-It Integrated Peripheral Controller
The IPC (Integrated Peripheral Controller) is the Oki proprietary ASIC which serves as the control
center of the Doc-It Controller. It is a highly integrated scan, print, FAX and copy control unit. The
IPC is programmed by either the i960 CPU or the PC-AT (via the HCC ASIC). The part supports
double or single bank DRAM access (the standard design is a double bank structure), 300 or 400
dpi printing, four mode scanning and supports international version DAAs for facsimile.
The key features are as follow:
Plastic quad flat pack-208 pins.
- 80960 Interface module.
- DMA controller function for the system.
- Timer and Interrupt controller logic.
- DAA interface logic.
- Memory controller logic.
- Programmable memory configuration table.
- Programmable memory I/O wait states.
- Programmable DRAM refresh control.
- Mirror image and inverted print scan functions.
- Maskable interrupts.
- Fully programmable timer control.
The IPC has seven major functional blocks. Each will be discussed separately.
80960 CPU Interface
The 80960 interface contains address selection, address latch, address decoder, and bus
handshake control logic. There are three basic address sources with the IPC chip:
· 80960 CPU
· Scanner Controller Module
· Printer Controller Module
Sources 2 and 3 are 32 bit internal IPC buses. Source 1 is the 32 bit wide bi-directional
address/data multiplexed bus which runs between the CPU, HCC and IPC. If the address source
is the HCC or i960 CPU, the IPC requires an external address latch signal (ALE) to latch the
address and free the bus for data transfer.
The IPC supports 5 categories of bus operation:
· Burst DRAM R/W bus cycle
- (address range 0000 0000 to 05FF FFFF and F000 0000 to FFFF FFFF)
· DRAM Read Modify Write bus cycle
- (address range 0600 0000 to 07FF FFFF)
· External device bus cycle
- (address range 0800 0000 to 0FFF FFFF)
· Fast I/O bus cycle