OKIDATA DOC-IT3000, Service Manual

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mode the address of the local bus memory is the result of offset address (programmed in the
Doc-It Controller Extended Memory Configuration Register plus the Extended Memory Starting
Address bits of the Extended Memory Configuration Register 1. This mode of operation is
supported via the Developers Toolkit software.
Local Bus Data Interface
This Doc-It Controller Local Data Bus Interface supports two types of access by the system; a
normal memory read/write access and a memory burst read/write access. The data bus is set
normally to be 32 bits wide. The address and data bus on the i960 side, between the i960, IPC
and HCC is a multiplexed address and data bus. All three parts use the CPUs status lines such as
ADS (Address/Data Status), ALE (Address Latch Enable), and DEN (Data Enable) to determine
the content of the bus. The CDASBEL signal can be pulled high to force the bus to 16 bits in
width.
In a normal memory read/write access, the Local Bus Data Interface block (in response to a AT
memory read/write cycle) directs the i960 CPU to get control of the local bus and send/receive
data to or from the PC system. The translation from 16 bit AT data size to/from i960 32 bit data
size is handled by the HCC.
In memory read/write burst mode, the HCC Local Bus Data Interface block will hold four 32 bit
data words in a buffer before transferring the data to the PC or Doc-It Controller board memory.
When the PC is writing to the Doc-It Controller, eight 16 bit data words will be written to the buffer
before the HCC requests a local burst cycle. In response to this request, the Doc-It Controller
board memory controller (in the IPC ASIC) will fetch four 32 bit words and write them to memory.
In response to a PC memory read cycle, the HCC will pull the IOCHRDY signal low on the bus to
indicate the board is busy. The IOCHRDY signal will remain in this state during the time while the
memory controller is transferring four 32 bit words to the HCCs buffer. When the data is available
the read cycle will complete. Burst mode can be dynamically controlled by the software as the
burst signal is an I/O port bit in the Oki Control Register 0.
EEPROM Interface
The EEPROM Interface is designed to accept an optional OKI MSM16811, 1K serial EEPROM
(128x8 mode). At this time, the EEPROM is not implemented on the standard product. The socket
is installed for future use, and all the circuitry is active. The EEPROM can be read or written via
the PC, through control ports (EEPROM Write Data Port, Write Address Port, Read Data Port,
Read Address Port).
Local Bus Arbiter
The Local Bus Arbiter is in charge of arbitrating requests for the local bus and generating the
HOLD signal to the i960. Printer requests, scanner requests and PC-AT requests share the local
bus with the i960. In response to one of these three requests, the HCC establishes a priority for
the request and generates the HOLD signal to the CPU. When the CPU grants the request to the
local bus, HLDA is returned and the HCC signals the requesting device that the bus is available.
The LPGNT and SCGNT signals are returned to the IPC, the requesting device. The grant signal
allows the requestor to drive local bus control signals. The PC host request is different from the
other two in that the request/grant also allows the local address and data bus to be controlled.
Programmable I/O Space
The PC Host I/O map given below show the I/O routes to the Doc-It Controller board. LPT1, LPT2
and LPT3 are mapped to standard PC-AT locations. The OKISELECT port is an I/O decode port
which can reside at 4 possible locations. These locations are set by jumpers on the board (refer to
Appendix A). The address decoded at this location provides the starting address for the
OkiControl ports.