NXP Semiconductors MC68CK16Z1, User Manual

Page: 321 / 501

M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS
USER’S MANUAL A-37
Table A-19 Low Voltage 16.78-MHz Background Debug Mode Timing
(V
DD
and V
DDSYN
= 2.7 to 3.6Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
NOTES:
1. All AC timing is shown with respect to V
IH
/V
IL
levels unless otherwise noted.
Num Characteristic Symbol Min Max Unit
B0 DSI Input Setup Time t
DSISU
15 — ns
B1 DSI Input Hold Time t
DSIH
15 — ns
B2 DSCLK Setup Time t
DSCSU
15 — ns
B3 DSCLK Hold Time t
DSCH
15 — ns
B4 DSO Delay Time t
DSOD
— 35 ns
B5 DSCLK Cycle Time t
DSCCYC
2 — t
cyc
B6 CLKOUT High to FREEZE Asserted/Negated t
FRZAN
— 50 ns
B7 CLKOUT High to IPIPE1 High Impedance t
IFZ
— 50 ns
B8 CLKOUT High to IPIPE1 Valid t
IF
— 50 ns
B9 DSCLK Low Time t
DSCLO
1 — t
cyc
B10 IPIPE1 High Impedance to FREEZE Asserted t
IPFA
TBD — t
cyc
B11 FREEZE Negated to IPIPE[0:1] Active t
FRIP
TBD — t
cyc
Table A-20 16.78-MHz Background Debug Mode Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
NOTES:
1. All AC timing is shown with respect to V
IH
/V
IL
levels unless otherwise noted.
Num Characteristic Symbol Min Max Unit
B0 DSI Input Setup Time t
DSISU
15 — ns
B1 DSI Input Hold Time t
DSIH
10 — ns
B2 DSCLK Setup Time t
DSCSU
15 — ns
B3 DSCLK Hold Time t
DSCH
10 — ns
B4 DSO Delay Time t
DSOD
— 25 ns
B5 DSCLK Cycle Time t
DSCCYC
2 — t
cyc
B6 CLKOUT High to FREEZE Asserted/Negated t
FRZAN
— 50 ns
B7 CLKOUT High to IPIPE1 High Impedance t
IFZ
— TBD ns
B8 CLKOUT High to IPIPE1 Valid t
IF
— TBD ns
B9 DSCLK Low Time t
DSCLO
1 — t
cyc
B10 IPIPE1 High Impedance to FREEZE Asserted t
IPFA
TBD — t
cyc
B11 FREEZE Negated to IPIPE[0:1] Active t
FRIP
TBD — t
cyc
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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